4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_flash.h"
27 #include "avr_watchdog.h"
28 #include "avr_extint.h"
29 #include "avr_ioport.h"
32 #include "avr_timer.h"
36 void m1280_init(struct avr_t * avr);
37 void m1280_reset(struct avr_t * avr);
41 #ifndef __AVR_ATmega1280__
42 #define __AVR_ATmega1280__
44 #include "avr/iom1280.h"
47 * This is a template for all of the 1280 devices, hopefully
53 avr_watchdog_t watchdog;
55 avr_ioport_t porta, portb, portc, portd, porte, portf, portg, porth, portj, portk, portl;
56 avr_uart_t uart0,uart1;
57 avr_uart_t uart2,uart3;
59 avr_timer_t timer0,timer1,timer2,timer3;
70 .rampz = RAMPZ, // extended program memory access
72 AVR_EEPROM_DECLARE(EE_READY_vect),
73 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
74 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
76 AVR_EXTINT_DECLARE(0, 'D', PD0),
77 AVR_EXTINT_DECLARE(1, 'D', PD1),
78 AVR_EXTINT_DECLARE(2, 'D', PD2),
79 AVR_EXTINT_DECLARE(3, 'D', PD3),
80 AVR_EXTINT_DECLARE(4, 'E', PE4),
81 AVR_EXTINT_DECLARE(5, 'E', PE5),
82 AVR_EXTINT_DECLARE(6, 'E', PE6),
83 AVR_EXTINT_DECLARE(7, 'E', PE7),
86 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
89 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
91 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
92 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
93 .vector = PCINT0_vect,
98 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
101 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
104 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
107 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
110 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
114 .name = 'H', .r_port = PORTH, .r_ddr = DDRH, .r_pin = PINH,
117 .name = 'J', .r_port = PORTJ, .r_ddr = DDRJ, .r_pin = PINJ,
120 .name = 'K', .r_port = PORTK, .r_ddr = DDRK, .r_pin = PINK,
123 .name = 'L', .r_port = PORTL, .r_ddr = DDRL, .r_pin = PINL,
127 .disabled = AVR_IO_REGBIT(PRR0,PRUSART0),
131 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
132 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
133 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
134 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), // 1 bits
142 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
143 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
144 .vector = USART0_RX_vect,
147 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
148 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
149 .vector = USART0_TX_vect,
152 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
153 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
154 .vector = USART0_UDRE_vect,
158 .disabled = AVR_IO_REGBIT(PRR1,PRUSART1),
162 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
163 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
164 .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
165 .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), // 1 bits
173 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
174 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
175 .vector = USART1_RX_vect,
178 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
179 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
180 .vector = USART1_TX_vect,
183 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
184 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
185 .vector = USART1_UDRE_vect,
190 .disabled = AVR_IO_REGBIT(PRR1,PRUSART2),
194 .txen = AVR_IO_REGBIT(UCSR2B, TXEN2),
195 .rxen = AVR_IO_REGBIT(UCSR2B, RXEN2),
196 .ucsz = AVR_IO_REGBITS(UCSR2C, UCSZ20, 0x3), // 2 bits
197 .ucsz2 = AVR_IO_REGBIT(UCSR2B, UCSZ22), // 1 bits
205 .enable = AVR_IO_REGBIT(UCSR2B, RXCIE2),
206 .raised = AVR_IO_REGBIT(UCSR2A, RXC2),
207 .vector = USART2_RX_vect,
210 .enable = AVR_IO_REGBIT(UCSR2B, TXCIE2),
211 .raised = AVR_IO_REGBIT(UCSR2A, TXC2),
212 .vector = USART2_TX_vect,
215 .enable = AVR_IO_REGBIT(UCSR2B, UDRIE2),
216 .raised = AVR_IO_REGBIT(UCSR2A, UDRE2),
217 .vector = USART2_UDRE_vect,
222 .disabled = AVR_IO_REGBIT(PRR1,PRUSART3),
226 .txen = AVR_IO_REGBIT(UCSR3B, TXEN3),
227 .rxen = AVR_IO_REGBIT(UCSR3B, RXEN3),
228 .ucsz = AVR_IO_REGBITS(UCSR3C, UCSZ30, 0x3), // 2 bits
229 .ucsz2 = AVR_IO_REGBIT(UCSR3B, UCSZ32), // 1 bits
237 .enable = AVR_IO_REGBIT(UCSR3B, RXCIE3),
238 .raised = AVR_IO_REGBIT(UCSR3A, RXC3),
239 .vector = USART3_RX_vect,
242 .enable = AVR_IO_REGBIT(UCSR3B, TXCIE3),
243 .raised = AVR_IO_REGBIT(UCSR3A, TXC3),
244 .vector = USART3_TX_vect,
247 .enable = AVR_IO_REGBIT(UCSR3B, UDRIE3),
248 .raised = AVR_IO_REGBIT(UCSR3A, UDRE3),
249 .vector = USART3_UDRE_vect,
254 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
255 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
256 AVR_IO_REGBIT(ADMUX, MUX4),AVR_IO_REGBIT(ADCSRB, MUX5),},
257 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
258 .ref_values = { [1] = ADC_VREF_AVCC, [2] = ADC_VREF_V110, [3] = ADC_VREF_V256 },
260 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
262 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
263 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
264 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
265 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
271 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
274 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
275 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
276 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
277 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
279 [ 8] = AVR_ADC_DIFF(0, 0, 10), [ 9] = AVR_ADC_DIFF(1, 0, 10),
280 [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
281 [12] = AVR_ADC_DIFF(2, 2, 10), [13] = AVR_ADC_DIFF(3, 2, 10),
282 [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
284 [16] = AVR_ADC_DIFF(0, 1, 1), [17] = AVR_ADC_DIFF(1, 1, 1),
285 [18] = AVR_ADC_DIFF(2, 1, 1), [19] = AVR_ADC_DIFF(3, 1, 1),
286 [20] = AVR_ADC_DIFF(4, 1, 1), [21] = AVR_ADC_DIFF(5, 1, 1),
287 [22] = AVR_ADC_DIFF(6, 1, 1), [23] = AVR_ADC_DIFF(7, 1, 1),
289 [24] = AVR_ADC_DIFF(0, 2, 1), [25] = AVR_ADC_DIFF(1, 2, 1),
290 [26] = AVR_ADC_DIFF(2, 2, 1), [27] = AVR_ADC_DIFF(3, 2, 1),
291 [28] = AVR_ADC_DIFF(4, 2, 1), [29] = AVR_ADC_DIFF(5, 2, 1),
293 [30] = AVR_ADC_REF(1100), // 1.1V
294 [31] = AVR_ADC_REF(0), // GND
296 [32] = AVR_ADC_SINGLE( 8), [33] = AVR_ADC_SINGLE( 9),
297 [34] = AVR_ADC_SINGLE(10), [35] = AVR_ADC_SINGLE(11),
298 [36] = AVR_ADC_SINGLE(12), [37] = AVR_ADC_SINGLE(13),
299 [38] = AVR_ADC_SINGLE(14), [39] = AVR_ADC_SINGLE(15),
300 /* TODO all the extra differential channels Datasheet page 296 */
304 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
305 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
311 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
313 [0] = AVR_TIMER_WGM_NORMAL8(),
314 [2] = AVR_TIMER_WGM_CTC(),
315 [3] = AVR_TIMER_WGM_FASTPWM8(),
316 [7] = AVR_TIMER_WGM_OCPWM(),
318 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
319 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
324 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
325 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
326 .vector = TIMER0_OVF_vect,
329 [AVR_TIMER_COMPA] = {
331 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
332 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
334 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
335 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
336 .vector = TIMER0_COMPA_vect,
339 [AVR_TIMER_COMPB] = {
341 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
342 .com_pin = AVR_IO_REGBIT(PORTG, PG5),
344 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
345 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
346 .vector = TIMER0_COMPB_vect,
353 .disabled = AVR_IO_REGBIT(PRR0,PRTIM1),
354 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
355 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
357 [0] = AVR_TIMER_WGM_NORMAL16(),
358 // TODO: 1 PWM phase correct 8bit
359 // 2 PWM phase correct 9bit
360 // 3 PWM phase correct 10bit
361 [4] = AVR_TIMER_WGM_CTC(),
362 [5] = AVR_TIMER_WGM_FASTPWM8(),
363 [6] = AVR_TIMER_WGM_FASTPWM9(),
364 [7] = AVR_TIMER_WGM_FASTPWM10(),
365 // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
366 [12] = AVR_TIMER_WGM_ICCTC(),
367 [14] = AVR_TIMER_WGM_ICPWM(),
368 [15] = AVR_TIMER_WGM_OCPWM(),
370 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
371 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
378 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
379 .icp = AVR_IO_REGBIT(PORTD, PD4),
382 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
383 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
384 .vector = TIMER1_OVF_vect,
387 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
388 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
389 .vector = TIMER1_CAPT_vect,
392 [AVR_TIMER_COMPA] = {
394 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
395 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
396 .com_pin = AVR_IO_REGBIT(PORTB, PB5),
398 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
399 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
400 .vector = TIMER1_COMPA_vect,
403 [AVR_TIMER_COMPB] = {
406 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
407 .com_pin = AVR_IO_REGBIT(PORTB, PB6),
409 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
410 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
411 .vector = TIMER1_COMPB_vect,
414 [AVR_TIMER_COMPC] = {
417 .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
418 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer0A
420 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1C),
421 .raised = AVR_IO_REGBIT(TIFR1, OCF1C),
422 .vector = TIMER1_COMPC_vect,
430 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
432 [0] = AVR_TIMER_WGM_NORMAL8(),
433 // TODO 1 pwm phase correct
434 [2] = AVR_TIMER_WGM_CTC(),
435 [3] = AVR_TIMER_WGM_FASTPWM8(),
436 [7] = AVR_TIMER_WGM_OCPWM(),
438 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
439 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
442 // asynchronous timer source bit.. if set, use 32khz frequency
443 .as2 = AVR_IO_REGBIT(ASSR, AS2),
446 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
447 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
448 .vector = TIMER2_OVF_vect,
451 [AVR_TIMER_COMPA] = {
453 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
454 .com_pin = AVR_IO_REGBIT(PORTB, PB4),
456 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
457 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
458 .vector = TIMER2_COMPA_vect,
461 // TIMER2_COMPB is only appeared in 1280
462 //[AVR_TIMER_COMPB] = {
464 // .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
465 // .com_pin = AVR_IO_REGBIT(PORTH, PH6),
467 // .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
468 // .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
469 // .vector = TIMER2_COMPB_vect,
476 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
477 AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
479 [0] = AVR_TIMER_WGM_NORMAL16(),
480 // TODO: 1 PWM phase correct 8bit
481 // 2 PWM phase correct 9bit
482 // 3 PWM phase correct 10bit
483 [4] = AVR_TIMER_WGM_CTC(),
484 [5] = AVR_TIMER_WGM_FASTPWM8(),
485 [6] = AVR_TIMER_WGM_FASTPWM9(),
486 [7] = AVR_TIMER_WGM_FASTPWM10(),
487 // TODO: 8 PWM phase and freq correct ICR
488 // 9 PWM phase and freq correct OCR
491 [12] = AVR_TIMER_WGM_ICCTC(),
492 [14] = AVR_TIMER_WGM_ICPWM(),
493 [15] = AVR_TIMER_WGM_OCPWM(),
495 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
496 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
503 .ices = AVR_IO_REGBIT(TCCR3B, ICES3),
504 .icp = AVR_IO_REGBIT(PORTE, PE7),
507 .enable = AVR_IO_REGBIT(TIMSK3, TOIE3),
508 .raised = AVR_IO_REGBIT(TIFR3, TOV3),
509 .vector = TIMER3_OVF_vect,
512 [AVR_TIMER_COMPA] = {
514 .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it
515 .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
516 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
518 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3A),
519 .raised = AVR_IO_REGBIT(TIFR3, OCF3A),
520 .vector = TIMER3_COMPA_vect,
523 [AVR_TIMER_COMPB] = {
526 .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
527 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
529 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3B),
530 .raised = AVR_IO_REGBIT(TIFR3, OCF3B),
531 .vector = TIMER3_COMPB_vect,
534 [AVR_TIMER_COMPC] = {
537 .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
538 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
540 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3C),
541 .raised = AVR_IO_REGBIT(TIFR3, OCF3C),
542 .vector = TIMER3_COMPC_vect,
547 .enable = AVR_IO_REGBIT(TIMSK3, ICIE3),
548 .raised = AVR_IO_REGBIT(TIFR3, ICF3),
549 .vector = TIMER3_CAPT_vect,
553 .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
559 .spe = AVR_IO_REGBIT(SPCR, SPE),
560 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
562 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
564 .enable = AVR_IO_REGBIT(SPCR, SPIE),
565 .raised = AVR_IO_REGBIT(SPSR, SPIF),
566 .vector = SPI_STC_vect,
579 .twen = AVR_IO_REGBIT(TWCR, TWEN),
580 .twea = AVR_IO_REGBIT(TWCR, TWEA),
581 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
582 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
583 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
585 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
586 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
589 .enable = AVR_IO_REGBIT(TWCR, TWIE),
590 .raised = AVR_IO_REGBIT(TWCR, TWINT),
597 static avr_t * make()
599 return &mcu_mega1280.core;
602 avr_kind_t mega1280 = {
603 .names = { "atmega1280" },
607 void m1280_init(struct avr_t * avr)
609 struct mcu_t * mcu = (struct mcu_t*)avr;
611 //printf("%s init\n", avr->mmcu);
613 avr_eeprom_init(avr, &mcu->eeprom);
614 avr_flash_init(avr, &mcu->selfprog);
615 avr_extint_init(avr, &mcu->extint);
616 avr_watchdog_init(avr, &mcu->watchdog);
617 avr_ioport_init(avr, &mcu->porta);
618 avr_ioport_init(avr, &mcu->portb);
619 avr_ioport_init(avr, &mcu->portc);
620 avr_ioport_init(avr, &mcu->portd);
621 avr_ioport_init(avr, &mcu->porte);
622 avr_ioport_init(avr, &mcu->portf);
623 avr_ioport_init(avr, &mcu->portg);
624 avr_ioport_init(avr, &mcu->porth);
625 avr_ioport_init(avr, &mcu->portj);
626 avr_ioport_init(avr, &mcu->portk);
627 avr_ioport_init(avr, &mcu->portl);
629 avr_uart_init(avr, &mcu->uart0);
630 avr_uart_init(avr, &mcu->uart1);
631 avr_adc_init(avr, &mcu->adc);
632 avr_timer_init(avr, &mcu->timer0);
633 avr_timer_init(avr, &mcu->timer1);
634 avr_timer_init(avr, &mcu->timer2);
635 avr_timer_init(avr, &mcu->timer3);
636 avr_spi_init(avr, &mcu->spi);
637 avr_twi_init(avr, &mcu->twi);
640 void m1280_reset(struct avr_t * avr)
642 // struct mcu_t * mcu = (struct mcu_t*)avr;