4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
23 #include "sim_core_declare.h"
24 #include "avr_eeprom.h"
25 #include "avr_flash.h"
26 #include "avr_watchdog.h"
27 #include "avr_extint.h"
28 #include "avr_ioport.h"
31 #include "avr_timer.h"
35 void m1281_init(struct avr_t * avr);
36 void m1281_reset(struct avr_t * avr);
40 #include "avr/iom1281.h"
43 * This is a template for all of the 1281 devices, hopefully
49 avr_watchdog_t watchdog;
51 avr_ioport_t porta, portb, portc, portd, porte, portf, portg;
52 avr_uart_t uart0,uart1;
54 avr_timer_t timer0,timer1,timer2,timer3;
65 .rampz = RAMPZ, // extended program memory access
67 AVR_EEPROM_DECLARE(EE_READY_vect),
68 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
69 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
71 AVR_EXTINT_MEGA_DECLARE(0, 'D', PD0, A),
72 AVR_EXTINT_MEGA_DECLARE(1, 'D', PD1, A),
73 AVR_EXTINT_MEGA_DECLARE(2, 'D', PD2, A),
74 AVR_EXTINT_MEGA_DECLARE(3, 'D', PD3, A),
75 AVR_EXTINT_MEGA_DECLARE(4, 'E', PE4, B),
76 AVR_EXTINT_MEGA_DECLARE(5, 'E', PE5, B),
77 AVR_EXTINT_MEGA_DECLARE(6, 'E', PE6, B),
78 AVR_EXTINT_MEGA_DECLARE(7, 'E', PE7, B),
81 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
84 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
86 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
87 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
88 .vector = PCINT0_vect,
93 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
96 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
99 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
102 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
105 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
109 .disabled = AVR_IO_REGBIT(PRR0,PRUSART0),
113 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
114 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
115 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
116 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), // 1 bits
124 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
125 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
126 .vector = USART0_RX_vect,
129 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
130 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
131 .vector = USART0_TX_vect,
134 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
135 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
136 .vector = USART0_UDRE_vect,
140 .disabled = AVR_IO_REGBIT(PRR1,PRUSART1),
144 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
145 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
146 .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
147 .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), // 1 bits
155 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
156 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
157 .vector = USART1_RX_vect,
160 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
161 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
162 .vector = USART1_TX_vect,
165 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
166 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
167 .vector = USART1_UDRE_vect,
172 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
173 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
174 AVR_IO_REGBIT(ADMUX, MUX4),},
175 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
176 .ref_values = { [1] = ADC_VREF_AVCC, [2] = ADC_VREF_V110, [3] = ADC_VREF_V256 },
178 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
180 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
181 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
182 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
183 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
189 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
192 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
193 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
194 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
195 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
197 [ 8] = AVR_ADC_DIFF(0, 0, 10), [ 9] = AVR_ADC_DIFF(1, 0, 10),
198 [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
199 [12] = AVR_ADC_DIFF(2, 2, 10), [13] = AVR_ADC_DIFF(3, 2, 10),
200 [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
202 [16] = AVR_ADC_DIFF(0, 1, 1), [17] = AVR_ADC_DIFF(1, 1, 1),
203 [18] = AVR_ADC_DIFF(2, 1, 1), [19] = AVR_ADC_DIFF(3, 1, 1),
204 [20] = AVR_ADC_DIFF(4, 1, 1), [21] = AVR_ADC_DIFF(5, 1, 1),
205 [22] = AVR_ADC_DIFF(6, 1, 1), [23] = AVR_ADC_DIFF(7, 1, 1),
207 [24] = AVR_ADC_DIFF(0, 2, 1), [25] = AVR_ADC_DIFF(1, 2, 1),
208 [26] = AVR_ADC_DIFF(2, 2, 1), [27] = AVR_ADC_DIFF(3, 2, 1),
209 [28] = AVR_ADC_DIFF(4, 2, 1), [29] = AVR_ADC_DIFF(5, 2, 1),
211 [30] = AVR_ADC_REF(1100), // 1.1V
212 [31] = AVR_ADC_REF(0), // GND
216 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
217 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
223 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
225 [0] = AVR_TIMER_WGM_NORMAL8(),
226 [2] = AVR_TIMER_WGM_CTC(),
227 [3] = AVR_TIMER_WGM_FASTPWM8(),
228 [7] = AVR_TIMER_WGM_OCPWM(),
230 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
231 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
236 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
237 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
238 .vector = TIMER0_OVF_vect,
241 [AVR_TIMER_COMPA] = {
243 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
244 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
246 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
247 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
248 .vector = TIMER0_COMPA_vect,
251 [AVR_TIMER_COMPB] = {
253 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
254 .com_pin = AVR_IO_REGBIT(PORTG, PG5),
256 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
257 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
258 .vector = TIMER0_COMPB_vect,
265 .disabled = AVR_IO_REGBIT(PRR0,PRTIM1),
266 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
267 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
269 [0] = AVR_TIMER_WGM_NORMAL16(),
270 // TODO: 1 PWM phase correct 8bit
271 // 2 PWM phase correct 9bit
272 // 3 PWM phase correct 10bit
273 [4] = AVR_TIMER_WGM_CTC(),
274 [5] = AVR_TIMER_WGM_FASTPWM8(),
275 [6] = AVR_TIMER_WGM_FASTPWM9(),
276 [7] = AVR_TIMER_WGM_FASTPWM10(),
277 // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
278 [12] = AVR_TIMER_WGM_ICCTC(),
279 [14] = AVR_TIMER_WGM_ICPWM(),
280 [15] = AVR_TIMER_WGM_OCPWM(),
282 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
283 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
290 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
291 .icp = AVR_IO_REGBIT(PORTD, PD4),
294 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
295 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
296 .vector = TIMER1_OVF_vect,
299 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
300 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
301 .vector = TIMER1_CAPT_vect,
304 [AVR_TIMER_COMPA] = {
306 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
307 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
308 .com_pin = AVR_IO_REGBIT(PORTB, PB5),
310 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
311 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
312 .vector = TIMER1_COMPA_vect,
315 [AVR_TIMER_COMPB] = {
318 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
319 .com_pin = AVR_IO_REGBIT(PORTB, PB6),
321 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
322 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
323 .vector = TIMER1_COMPB_vect,
326 [AVR_TIMER_COMPC] = {
329 .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
330 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer0A
332 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1C),
333 .raised = AVR_IO_REGBIT(TIFR1, OCF1C),
334 .vector = TIMER1_COMPC_vect,
342 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
344 [0] = AVR_TIMER_WGM_NORMAL8(),
345 // TODO 1 pwm phase correct
346 [2] = AVR_TIMER_WGM_CTC(),
347 [3] = AVR_TIMER_WGM_FASTPWM8(),
348 [7] = AVR_TIMER_WGM_OCPWM(),
350 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
351 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
354 // asynchronous timer source bit.. if set, use 32khz frequency
355 .as2 = AVR_IO_REGBIT(ASSR, AS2),
358 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
359 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
360 .vector = TIMER2_OVF_vect,
363 [AVR_TIMER_COMPA] = {
365 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
366 .com_pin = AVR_IO_REGBIT(PORTB, PB4),
368 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
369 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
370 .vector = TIMER2_COMPA_vect,
373 // TIMER2_COMPB is only appeared in 1280
374 //[AVR_TIMER_COMPB] = {
376 // .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
377 // .com_pin = AVR_IO_REGBIT(PORTH, PH6),
379 // .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
380 // .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
381 // .vector = TIMER2_COMPB_vect,
388 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
389 AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
391 [0] = AVR_TIMER_WGM_NORMAL16(),
392 // TODO: 1 PWM phase correct 8bit
393 // 2 PWM phase correct 9bit
394 // 3 PWM phase correct 10bit
395 [4] = AVR_TIMER_WGM_CTC(),
396 [5] = AVR_TIMER_WGM_FASTPWM8(),
397 [6] = AVR_TIMER_WGM_FASTPWM9(),
398 [7] = AVR_TIMER_WGM_FASTPWM10(),
399 // TODO: 8 PWM phase and freq correct ICR
400 // 9 PWM phase and freq correct OCR
403 [12] = AVR_TIMER_WGM_ICCTC(),
404 [14] = AVR_TIMER_WGM_ICPWM(),
405 [15] = AVR_TIMER_WGM_OCPWM(),
407 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
408 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
415 .ices = AVR_IO_REGBIT(TCCR3B, ICES3),
416 .icp = AVR_IO_REGBIT(PORTE, PE7),
419 .enable = AVR_IO_REGBIT(TIMSK3, TOIE3),
420 .raised = AVR_IO_REGBIT(TIFR3, TOV3),
421 .vector = TIMER3_OVF_vect,
424 [AVR_TIMER_COMPA] = {
426 .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it
427 .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
428 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
430 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3A),
431 .raised = AVR_IO_REGBIT(TIFR3, OCF3A),
432 .vector = TIMER3_COMPA_vect,
435 [AVR_TIMER_COMPB] = {
438 .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
439 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
441 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3B),
442 .raised = AVR_IO_REGBIT(TIFR3, OCF3B),
443 .vector = TIMER3_COMPB_vect,
446 [AVR_TIMER_COMPC] = {
449 .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
450 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
452 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3C),
453 .raised = AVR_IO_REGBIT(TIFR3, OCF3C),
454 .vector = TIMER3_COMPC_vect,
459 .enable = AVR_IO_REGBIT(TIMSK3, ICIE3),
460 .raised = AVR_IO_REGBIT(TIFR3, ICF3),
461 .vector = TIMER3_CAPT_vect,
465 .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
471 .spe = AVR_IO_REGBIT(SPCR, SPE),
472 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
474 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
476 .enable = AVR_IO_REGBIT(SPCR, SPIE),
477 .raised = AVR_IO_REGBIT(SPSR, SPIF),
478 .vector = SPI_STC_vect,
491 .twen = AVR_IO_REGBIT(TWCR, TWEN),
492 .twea = AVR_IO_REGBIT(TWCR, TWEA),
493 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
494 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
495 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
497 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
498 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
501 .enable = AVR_IO_REGBIT(TWCR, TWIE),
502 .raised = AVR_IO_REGBIT(TWCR, TWINT),
510 static avr_t * make()
512 return avr_core_allocate(&mcu_mega1281.core, sizeof(struct mcu_t));
515 avr_kind_t mega1281 = {
516 .names = { "atmega1281" },
520 void m1281_init(struct avr_t * avr)
522 struct mcu_t * mcu = (struct mcu_t*)avr;
524 avr_eeprom_init(avr, &mcu->eeprom);
525 avr_flash_init(avr, &mcu->selfprog);
526 avr_extint_init(avr, &mcu->extint);
527 avr_watchdog_init(avr, &mcu->watchdog);
528 avr_ioport_init(avr, &mcu->porta);
529 avr_ioport_init(avr, &mcu->portb);
530 avr_ioport_init(avr, &mcu->portc);
531 avr_ioport_init(avr, &mcu->portd);
532 avr_ioport_init(avr, &mcu->porte);
533 avr_ioport_init(avr, &mcu->portf);
534 avr_ioport_init(avr, &mcu->portg);
535 avr_uart_init(avr, &mcu->uart0);
536 avr_uart_init(avr, &mcu->uart1);
537 avr_adc_init(avr, &mcu->adc);
538 avr_timer_init(avr, &mcu->timer0);
539 avr_timer_init(avr, &mcu->timer1);
540 avr_timer_init(avr, &mcu->timer2);
541 avr_timer_init(avr, &mcu->timer3);
542 avr_spi_init(avr, &mcu->spi);
543 avr_twi_init(avr, &mcu->twi);
546 void m1281_reset(struct avr_t * avr)
548 // struct mcu_t * mcu = (struct mcu_t*)avr;