4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_flash.h"
27 #include "avr_watchdog.h"
28 #include "avr_extint.h"
29 #include "avr_ioport.h"
32 #include "avr_timer.h"
36 void m1281_init(struct avr_t * avr);
37 void m1281_reset(struct avr_t * avr);
41 #include "avr/iom1281.h"
44 * This is a template for all of the 1281 devices, hopefully
50 avr_watchdog_t watchdog;
52 avr_ioport_t porta, portb, portc, portd, porte, portf, portg;
53 avr_uart_t uart0,uart1;
55 avr_timer_t timer0,timer1,timer2,timer3;
66 .rampz = RAMPZ, // extended program memory access
68 AVR_EEPROM_DECLARE(EE_READY_vect),
69 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
70 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
72 AVR_EXTINT_DECLARE(0, 'D', PD0),
73 AVR_EXTINT_DECLARE(1, 'D', PD1),
74 AVR_EXTINT_DECLARE(2, 'D', PD2),
75 AVR_EXTINT_DECLARE(3, 'D', PD3),
76 AVR_EXTINT_DECLARE(4, 'E', PE4),
77 AVR_EXTINT_DECLARE(5, 'E', PE5),
78 AVR_EXTINT_DECLARE(6, 'E', PE6),
79 AVR_EXTINT_DECLARE(7, 'E', PE7),
82 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
85 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
87 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
88 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
89 .vector = PCINT0_vect,
94 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
97 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
100 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
103 .name = 'F', .r_port = PORTF, .r_ddr = DDRF, .r_pin = PINF,
106 .name = 'G', .r_port = PORTG, .r_ddr = DDRG, .r_pin = PING,
110 .disabled = AVR_IO_REGBIT(PRR0,PRUSART0),
114 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
115 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
116 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
117 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), // 1 bits
125 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
126 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
127 .vector = USART0_RX_vect,
130 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
131 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
132 .vector = USART0_TX_vect,
135 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
136 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
137 .vector = USART0_UDRE_vect,
141 .disabled = AVR_IO_REGBIT(PRR1,PRUSART1),
145 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
146 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
147 .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
148 .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), // 1 bits
156 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
157 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
158 .vector = USART1_RX_vect,
161 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
162 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
163 .vector = USART1_TX_vect,
166 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
167 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
168 .vector = USART1_UDRE_vect,
173 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
174 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
175 AVR_IO_REGBIT(ADMUX, MUX4),},
176 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
177 .ref_values = { [1] = ADC_VREF_AVCC, [2] = ADC_VREF_V110, [3] = ADC_VREF_V256 },
179 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
181 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
182 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
183 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
184 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
190 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
193 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
194 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
195 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
196 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
198 [ 8] = AVR_ADC_DIFF(0, 0, 10), [ 9] = AVR_ADC_DIFF(1, 0, 10),
199 [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
200 [12] = AVR_ADC_DIFF(2, 2, 10), [13] = AVR_ADC_DIFF(3, 2, 10),
201 [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
203 [16] = AVR_ADC_DIFF(0, 1, 1), [17] = AVR_ADC_DIFF(1, 1, 1),
204 [18] = AVR_ADC_DIFF(2, 1, 1), [19] = AVR_ADC_DIFF(3, 1, 1),
205 [20] = AVR_ADC_DIFF(4, 1, 1), [21] = AVR_ADC_DIFF(5, 1, 1),
206 [22] = AVR_ADC_DIFF(6, 1, 1), [23] = AVR_ADC_DIFF(7, 1, 1),
208 [24] = AVR_ADC_DIFF(0, 2, 1), [25] = AVR_ADC_DIFF(1, 2, 1),
209 [26] = AVR_ADC_DIFF(2, 2, 1), [27] = AVR_ADC_DIFF(3, 2, 1),
210 [28] = AVR_ADC_DIFF(4, 2, 1), [29] = AVR_ADC_DIFF(5, 2, 1),
212 [30] = AVR_ADC_REF(1100), // 1.1V
213 [31] = AVR_ADC_REF(0), // GND
217 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
218 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
224 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
226 [0] = AVR_TIMER_WGM_NORMAL8(),
227 [2] = AVR_TIMER_WGM_CTC(),
228 [3] = AVR_TIMER_WGM_FASTPWM8(),
229 [7] = AVR_TIMER_WGM_OCPWM(),
231 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
232 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
237 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
238 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
239 .vector = TIMER0_OVF_vect,
242 [AVR_TIMER_COMPA] = {
244 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
245 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer1C
247 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
248 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
249 .vector = TIMER0_COMPA_vect,
252 [AVR_TIMER_COMPB] = {
254 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
255 .com_pin = AVR_IO_REGBIT(PORTG, PG5),
257 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
258 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
259 .vector = TIMER0_COMPB_vect,
266 .disabled = AVR_IO_REGBIT(PRR0,PRTIM1),
267 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
268 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
270 [0] = AVR_TIMER_WGM_NORMAL16(),
271 // TODO: 1 PWM phase correct 8bit
272 // 2 PWM phase correct 9bit
273 // 3 PWM phase correct 10bit
274 [4] = AVR_TIMER_WGM_CTC(),
275 [5] = AVR_TIMER_WGM_FASTPWM8(),
276 [6] = AVR_TIMER_WGM_FASTPWM9(),
277 [7] = AVR_TIMER_WGM_FASTPWM10(),
278 // TODO: 8, 9 PWM phase and freq correct ICR & 10, 11
279 [12] = AVR_TIMER_WGM_ICCTC(),
280 [14] = AVR_TIMER_WGM_ICPWM(),
281 [15] = AVR_TIMER_WGM_OCPWM(),
283 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
284 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
291 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
292 .icp = AVR_IO_REGBIT(PORTD, PD4),
295 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
296 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
297 .vector = TIMER1_OVF_vect,
300 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
301 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
302 .vector = TIMER1_CAPT_vect,
305 [AVR_TIMER_COMPA] = {
307 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
308 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
309 .com_pin = AVR_IO_REGBIT(PORTB, PB5),
311 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
312 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
313 .vector = TIMER1_COMPA_vect,
316 [AVR_TIMER_COMPB] = {
319 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
320 .com_pin = AVR_IO_REGBIT(PORTB, PB6),
322 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
323 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
324 .vector = TIMER1_COMPB_vect,
327 [AVR_TIMER_COMPC] = {
330 .com = AVR_IO_REGBITS(TCCR1A, COM1C0, 0x3),
331 .com_pin = AVR_IO_REGBIT(PORTB, PB7), // same as timer0A
333 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1C),
334 .raised = AVR_IO_REGBIT(TIFR1, OCF1C),
335 .vector = TIMER1_COMPC_vect,
343 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
345 [0] = AVR_TIMER_WGM_NORMAL8(),
346 // TODO 1 pwm phase correct
347 [2] = AVR_TIMER_WGM_CTC(),
348 [3] = AVR_TIMER_WGM_FASTPWM8(),
349 [7] = AVR_TIMER_WGM_OCPWM(),
351 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
352 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
355 // asynchronous timer source bit.. if set, use 32khz frequency
356 .as2 = AVR_IO_REGBIT(ASSR, AS2),
359 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
360 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
361 .vector = TIMER2_OVF_vect,
364 [AVR_TIMER_COMPA] = {
366 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
367 .com_pin = AVR_IO_REGBIT(PORTB, PB4),
369 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
370 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
371 .vector = TIMER2_COMPA_vect,
374 // TIMER2_COMPB is only appeared in 1280
375 //[AVR_TIMER_COMPB] = {
377 // .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
378 // .com_pin = AVR_IO_REGBIT(PORTH, PH6),
380 // .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
381 // .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
382 // .vector = TIMER2_COMPB_vect,
389 .wgm = { AVR_IO_REGBIT(TCCR3A, WGM30), AVR_IO_REGBIT(TCCR3A, WGM31),
390 AVR_IO_REGBIT(TCCR3B, WGM32), AVR_IO_REGBIT(TCCR3B, WGM33) },
392 [0] = AVR_TIMER_WGM_NORMAL16(),
393 // TODO: 1 PWM phase correct 8bit
394 // 2 PWM phase correct 9bit
395 // 3 PWM phase correct 10bit
396 [4] = AVR_TIMER_WGM_CTC(),
397 [5] = AVR_TIMER_WGM_FASTPWM8(),
398 [6] = AVR_TIMER_WGM_FASTPWM9(),
399 [7] = AVR_TIMER_WGM_FASTPWM10(),
400 // TODO: 8 PWM phase and freq correct ICR
401 // 9 PWM phase and freq correct OCR
404 [12] = AVR_TIMER_WGM_ICCTC(),
405 [14] = AVR_TIMER_WGM_ICPWM(),
406 [15] = AVR_TIMER_WGM_OCPWM(),
408 .cs = { AVR_IO_REGBIT(TCCR3B, CS30), AVR_IO_REGBIT(TCCR3B, CS31), AVR_IO_REGBIT(TCCR3B, CS32) },
409 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* TODO: 2 External clocks */},
416 .ices = AVR_IO_REGBIT(TCCR3B, ICES3),
417 .icp = AVR_IO_REGBIT(PORTE, PE7),
420 .enable = AVR_IO_REGBIT(TIMSK3, TOIE3),
421 .raised = AVR_IO_REGBIT(TIFR3, TOV3),
422 .vector = TIMER3_OVF_vect,
425 [AVR_TIMER_COMPA] = {
427 .r_ocrh = OCR3AH, // 16 bits timers have two bytes of it
428 .com = AVR_IO_REGBITS(TCCR3A, COM3A0, 0x3),
429 .com_pin = AVR_IO_REGBIT(PORTE, PE3),
431 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3A),
432 .raised = AVR_IO_REGBIT(TIFR3, OCF3A),
433 .vector = TIMER3_COMPA_vect,
436 [AVR_TIMER_COMPB] = {
439 .com = AVR_IO_REGBITS(TCCR3A, COM3B0, 0x3),
440 .com_pin = AVR_IO_REGBIT(PORTE, PE4),
442 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3B),
443 .raised = AVR_IO_REGBIT(TIFR3, OCF3B),
444 .vector = TIMER3_COMPB_vect,
447 [AVR_TIMER_COMPC] = {
450 .com = AVR_IO_REGBITS(TCCR3A, COM3C0, 0x3),
451 .com_pin = AVR_IO_REGBIT(PORTE, PE5),
453 .enable = AVR_IO_REGBIT(TIMSK3, OCIE3C),
454 .raised = AVR_IO_REGBIT(TIFR3, OCF3C),
455 .vector = TIMER3_COMPC_vect,
460 .enable = AVR_IO_REGBIT(TIMSK3, ICIE3),
461 .raised = AVR_IO_REGBIT(TIFR3, ICF3),
462 .vector = TIMER3_CAPT_vect,
466 .disabled = AVR_IO_REGBIT(PRR0,PRSPI),
472 .spe = AVR_IO_REGBIT(SPCR, SPE),
473 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
475 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
477 .enable = AVR_IO_REGBIT(SPCR, SPIE),
478 .raised = AVR_IO_REGBIT(SPSR, SPIF),
479 .vector = SPI_STC_vect,
492 .twen = AVR_IO_REGBIT(TWCR, TWEN),
493 .twea = AVR_IO_REGBIT(TWCR, TWEA),
494 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
495 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
496 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
498 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
499 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
502 .enable = AVR_IO_REGBIT(TWCR, TWIE),
503 .raised = AVR_IO_REGBIT(TWCR, TWINT),
510 static avr_t * make()
512 return &mcu_mega1281.core;
515 avr_kind_t mega1281 = {
516 .names = { "atmega1281" },
520 void m1281_init(struct avr_t * avr)
522 struct mcu_t * mcu = (struct mcu_t*)avr;
524 printf("%s init\n", avr->mmcu);
526 avr_eeprom_init(avr, &mcu->eeprom);
527 avr_flash_init(avr, &mcu->selfprog);
528 avr_extint_init(avr, &mcu->extint);
529 avr_watchdog_init(avr, &mcu->watchdog);
530 avr_ioport_init(avr, &mcu->porta);
531 avr_ioport_init(avr, &mcu->portb);
532 avr_ioport_init(avr, &mcu->portc);
533 avr_ioport_init(avr, &mcu->portd);
534 avr_ioport_init(avr, &mcu->porte);
535 avr_ioport_init(avr, &mcu->portf);
536 avr_ioport_init(avr, &mcu->portg);
537 avr_uart_init(avr, &mcu->uart0);
538 avr_uart_init(avr, &mcu->uart1);
539 avr_adc_init(avr, &mcu->adc);
540 avr_timer_init(avr, &mcu->timer0);
541 avr_timer_init(avr, &mcu->timer1);
542 avr_timer_init(avr, &mcu->timer2);
543 avr_timer_init(avr, &mcu->timer3);
544 avr_spi_init(avr, &mcu->spi);
545 avr_twi_init(avr, &mcu->twi);
548 void m1281_reset(struct avr_t * avr)
550 // struct mcu_t * mcu = (struct mcu_t*)avr;