4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 #include </usr/include/stdio.h>
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_extint.h"
27 #include "avr_ioport.h"
29 #include "avr_timer8.h"
35 #include "avr/iom644.h"
37 static void init(struct avr_t * avr);
38 static void reset(struct avr_t * avr);
45 avr_ioport_t porta, portb, portc, portd;
46 avr_uart_t uart0,uart1;
47 avr_timer8_t timer0,timer2;
58 AVR_EEPROM_DECLARE(EE_READY_vect),
60 AVR_EXTINT_DECLARE(0, 'D', PD2),
61 AVR_EXTINT_DECLARE(1, 'D', PD3),
62 AVR_EXTINT_DECLARE(2, 'B', PB3),
65 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
67 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
68 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
69 .vector = PCINT0_vect,
74 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
76 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
77 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
78 .vector = PCINT1_vect,
83 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
85 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
86 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
87 .vector = PCINT2_vect,
92 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
94 .enable = AVR_IO_REGBIT(PCICR, PCIE3),
95 .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
96 .vector = PCINT3_vect,
102 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
106 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
107 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
115 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
116 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
117 .vector = USART0_RX_vect,
120 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
121 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
122 .vector = USART0_TX_vect,
125 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
126 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
127 .vector = USART0_UDRE_vect,
131 .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
135 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
136 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
144 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
145 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
146 .vector = USART1_RX_vect,
149 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
150 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
151 .vector = USART1_TX_vect,
154 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
155 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
156 .vector = USART1_UDRE_vect,
162 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
163 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
164 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
171 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
172 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
173 .vector = TIMER0_OVF_vect,
176 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
177 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
178 .vector = TIMER0_COMPA_vect,
181 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
182 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
183 .vector = TIMER0_COMPB_vect,
188 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
189 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
190 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
196 // asynchronous timer source bit.. if set, use 32khz frequency
197 .as2 = AVR_IO_REGBIT(ASSR, AS2),
200 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
201 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
202 .vector = TIMER2_OVF_vect,
205 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
206 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
207 .vector = TIMER2_COMPA_vect,
210 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
211 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
212 .vector = TIMER2_COMPB_vect,
216 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
222 .spe = AVR_IO_REGBIT(SPCR, SPE),
223 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
225 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
227 .enable = AVR_IO_REGBIT(SPCR, SPIE),
228 .raised = AVR_IO_REGBIT(SPSR, SPIF),
229 .vector = SPI_STC_vect,
234 .disabled = AVR_IO_REGBIT(PRR,PRTWI),
243 .twen = AVR_IO_REGBIT(TWCR, TWEN),
244 .twea = AVR_IO_REGBIT(TWCR, TWEA),
245 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
246 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
247 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
249 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
250 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
253 .enable = AVR_IO_REGBIT(TWCR, TWIE),
254 .raised = AVR_IO_REGBIT(TWSR, TWINT),
261 static avr_t * make()
266 avr_kind_t mega644 = {
267 .names = { "atmega644", "atmega644p" },
271 static void init(struct avr_t * avr)
273 struct mcu_t * mcu = (struct mcu_t*)avr;
275 printf("%s init\n", avr->mmcu);
277 avr_eeprom_init(avr, &mcu->eeprom);
278 avr_extint_init(avr, &mcu->extint);
279 avr_ioport_init(avr, &mcu->porta);
280 avr_ioport_init(avr, &mcu->portb);
281 avr_ioport_init(avr, &mcu->portc);
282 avr_ioport_init(avr, &mcu->portd);
283 avr_uart_init(avr, &mcu->uart0);
284 avr_uart_init(avr, &mcu->uart1);
285 avr_timer8_init(avr, &mcu->timer0);
286 avr_timer8_init(avr, &mcu->timer2);
287 avr_spi_init(avr, &mcu->spi);
288 avr_twi_init(avr, &mcu->twi);
291 static void reset(struct avr_t * avr)
293 // struct mcu_t * mcu = (struct mcu_t*)avr;