4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 #include </usr/include/stdio.h>
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_ioport.h"
28 #include "avr_timer8.h"
32 #include "avr/iom644.h"
34 static void init(struct avr_t * avr);
35 static void reset(struct avr_t * avr);
41 avr_ioport_t porta, portb, portc, portd;
42 avr_uart_t uart0,uart1;
43 avr_timer8_t timer0,timer2;
52 AVR_EEPROM_DECLARE(EE_READY_vect),
54 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
56 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
57 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
58 .vector = PCINT0_vect,
63 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
65 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
66 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
67 .vector = PCINT1_vect,
72 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
74 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
75 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
76 .vector = PCINT2_vect,
81 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
83 .enable = AVR_IO_REGBIT(PCICR, PCIE3),
84 .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
85 .vector = PCINT3_vect,
91 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
95 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
96 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
104 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
105 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
106 .vector = USART0_RX_vect,
109 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
110 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
111 .vector = USART0_TX_vect,
114 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
115 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
116 .vector = USART0_UDRE_vect,
120 .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
124 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
125 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
133 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
134 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
135 .vector = USART1_RX_vect,
138 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
139 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
140 .vector = USART1_TX_vect,
143 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
144 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
145 .vector = USART1_UDRE_vect,
151 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
152 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
153 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
160 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
161 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
162 .vector = TIMER0_OVF_vect,
165 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
166 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
167 .vector = TIMER0_COMPA_vect,
170 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
171 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
172 .vector = TIMER0_COMPB_vect,
177 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
178 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
179 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
185 // asynchronous timer source bit.. if set, use 32khz frequency
186 .as2 = AVR_IO_REGBIT(ASSR, AS2),
189 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
190 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
191 .vector = TIMER2_OVF_vect,
194 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
195 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
196 .vector = TIMER2_COMPA_vect,
199 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
200 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
201 .vector = TIMER2_COMPB_vect,
206 static avr_t * make()
211 avr_kind_t mega644 = {
212 .names = { "atmega644", "atmega644p" },
216 static void init(struct avr_t * avr)
218 struct mcu_t * mcu = (struct mcu_t*)avr;
220 printf("%s init\n", avr->mmcu);
222 avr_eeprom_init(avr, &mcu->eeprom);
223 avr_ioport_init(avr, &mcu->porta);
224 avr_ioport_init(avr, &mcu->portb);
225 avr_ioport_init(avr, &mcu->portc);
226 avr_ioport_init(avr, &mcu->portd);
227 avr_uart_init(avr, &mcu->uart0);
228 avr_uart_init(avr, &mcu->uart1);
229 avr_timer8_init(avr, &mcu->timer0);
230 avr_timer8_init(avr, &mcu->timer2);
233 static void reset(struct avr_t * avr)
235 // struct mcu_t * mcu = (struct mcu_t*)avr;