4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 #include </usr/include/stdio.h>
24 #include "sim_core_declare.h"
25 #include "avr_eeprom.h"
26 #include "avr_ioport.h"
28 #include "avr_timer8.h"
33 #include "avr/iom644.h"
35 static void init(struct avr_t * avr);
36 static void reset(struct avr_t * avr);
42 avr_ioport_t porta, portb, portc, portd;
43 avr_uart_t uart0,uart1;
44 avr_timer8_t timer0,timer2;
54 AVR_EEPROM_DECLARE(EE_READY_vect),
56 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
58 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
59 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
60 .vector = PCINT0_vect,
65 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
67 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
68 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
69 .vector = PCINT1_vect,
74 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
76 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
77 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
78 .vector = PCINT2_vect,
83 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
85 .enable = AVR_IO_REGBIT(PCICR, PCIE3),
86 .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
87 .vector = PCINT3_vect,
93 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
97 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
98 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
106 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
107 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
108 .vector = USART0_RX_vect,
111 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
112 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
113 .vector = USART0_TX_vect,
116 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
117 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
118 .vector = USART0_UDRE_vect,
122 .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
126 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
127 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
135 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
136 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
137 .vector = USART1_RX_vect,
140 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
141 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
142 .vector = USART1_TX_vect,
145 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
146 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
147 .vector = USART1_UDRE_vect,
153 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
154 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
155 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
162 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
163 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
164 .vector = TIMER0_OVF_vect,
167 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
168 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
169 .vector = TIMER0_COMPA_vect,
172 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
173 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
174 .vector = TIMER0_COMPB_vect,
179 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
180 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
181 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
187 // asynchronous timer source bit.. if set, use 32khz frequency
188 .as2 = AVR_IO_REGBIT(ASSR, AS2),
191 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
192 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
193 .vector = TIMER2_OVF_vect,
196 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
197 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
198 .vector = TIMER2_COMPA_vect,
201 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
202 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
203 .vector = TIMER2_COMPB_vect,
207 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
213 .spe = AVR_IO_REGBIT(SPCR, SPE),
214 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
216 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
218 .enable = AVR_IO_REGBIT(SPCR, SPIE),
219 .raised = AVR_IO_REGBIT(SPSR, SPIF),
220 .vector = SPI_STC_vect,
225 static avr_t * make()
230 avr_kind_t mega644 = {
231 .names = { "atmega644", "atmega644p" },
235 static void init(struct avr_t * avr)
237 struct mcu_t * mcu = (struct mcu_t*)avr;
239 printf("%s init\n", avr->mmcu);
241 avr_eeprom_init(avr, &mcu->eeprom);
242 avr_ioport_init(avr, &mcu->porta);
243 avr_ioport_init(avr, &mcu->portb);
244 avr_ioport_init(avr, &mcu->portc);
245 avr_ioport_init(avr, &mcu->portd);
246 avr_uart_init(avr, &mcu->uart0);
247 avr_uart_init(avr, &mcu->uart1);
248 avr_timer8_init(avr, &mcu->timer0);
249 avr_timer8_init(avr, &mcu->timer2);
250 avr_spi_init(avr, &mcu->spi);
253 static void reset(struct avr_t * avr)
255 // struct mcu_t * mcu = (struct mcu_t*)avr;