4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __SIM_MEGAX4_H__
23 #define __SIM_MEGAX4_H__
26 #include "sim_core_declare.h"
27 #include "avr_eeprom.h"
28 #include "avr_flash.h"
29 #include "avr_watchdog.h"
30 #include "avr_extint.h"
31 #include "avr_ioport.h"
34 #include "avr_timer.h"
38 void mx4_init(struct avr_t * avr);
39 void mx4_reset(struct avr_t * avr);
42 * This is a template for all of the x4 devices, hopefully
48 avr_watchdog_t watchdog;
50 avr_ioport_t porta, portb, portc, portd;
51 avr_uart_t uart0,uart1;
53 avr_timer_t timer0,timer1,timer2;
61 #error SIM_MMCU is not declared
64 const struct mcu_t SIM_CORENAME = {
72 AVR_EEPROM_DECLARE(EE_READY_vect),
73 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
74 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
76 AVR_EXTINT_DECLARE(0, 'D', PD2),
77 AVR_EXTINT_DECLARE(1, 'D', PD3),
78 AVR_EXTINT_DECLARE(2, 'B', PB3),
81 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
83 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
84 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
85 .vector = PCINT0_vect,
90 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
92 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
93 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
94 .vector = PCINT1_vect,
99 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
101 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
102 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
103 .vector = PCINT2_vect,
108 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
110 .enable = AVR_IO_REGBIT(PCICR, PCIE3),
111 .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
112 .vector = PCINT3_vect,
118 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
122 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
123 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
124 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
125 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), // 1 bits
133 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
134 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
135 .vector = USART0_RX_vect,
138 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
139 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
140 .vector = USART0_TX_vect,
143 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
144 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
145 .vector = USART0_UDRE_vect,
149 .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
153 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
154 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
155 .ucsz = AVR_IO_REGBITS(UCSR1C, UCSZ10, 0x3), // 2 bits
156 .ucsz2 = AVR_IO_REGBIT(UCSR1B, UCSZ12), // 1 bits
164 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
165 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
166 .vector = USART1_RX_vect,
169 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
170 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
171 .vector = USART1_TX_vect,
174 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
175 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
176 .vector = USART1_UDRE_vect,
181 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
182 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
183 AVR_IO_REGBIT(ADMUX, MUX4),},
184 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
185 .ref_values = { [1] = ADC_VREF_AVCC, [2] = ADC_VREF_V110, [3] = ADC_VREF_V256 },
187 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
189 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
190 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
191 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
192 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
198 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
201 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
202 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
203 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
204 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
206 [ 8] = AVR_ADC_DIFF(0, 0, 10), [ 9] = AVR_ADC_DIFF(1, 0, 10),
207 [10] = AVR_ADC_DIFF(0, 0, 200), [11] = AVR_ADC_DIFF(1, 0, 200),
208 [12] = AVR_ADC_DIFF(2, 2, 10), [13] = AVR_ADC_DIFF(3, 2, 10),
209 [14] = AVR_ADC_DIFF(2, 2, 200), [15] = AVR_ADC_DIFF(3, 2, 200),
211 [16] = AVR_ADC_DIFF(0, 1, 1), [17] = AVR_ADC_DIFF(1, 1, 1),
212 [18] = AVR_ADC_DIFF(2, 1, 1), [19] = AVR_ADC_DIFF(3, 1, 1),
213 [20] = AVR_ADC_DIFF(4, 1, 1), [21] = AVR_ADC_DIFF(5, 1, 1),
214 [22] = AVR_ADC_DIFF(6, 1, 1), [23] = AVR_ADC_DIFF(7, 1, 1),
216 [24] = AVR_ADC_DIFF(0, 2, 1), [25] = AVR_ADC_DIFF(1, 2, 1),
217 [26] = AVR_ADC_DIFF(2, 2, 1), [27] = AVR_ADC_DIFF(3, 2, 1),
218 [28] = AVR_ADC_DIFF(4, 2, 1), [29] = AVR_ADC_DIFF(5, 2, 1),
220 [30] = AVR_ADC_REF(1100), // 1.1V
221 [31] = AVR_ADC_REF(0), // GND
225 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
226 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
232 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
234 [0] = AVR_TIMER_WGM_NORMAL8(),
235 [2] = AVR_TIMER_WGM_CTC(),
236 [3] = AVR_TIMER_WGM_FASTPWM8(),
237 [7] = AVR_TIMER_WGM_OCPWM(),
239 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
240 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
245 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
246 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
247 .vector = TIMER0_OVF_vect,
250 [AVR_TIMER_COMPA] = {
252 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
253 .com_pin = AVR_IO_REGBIT(PORTB, 3),
255 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
256 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
257 .vector = TIMER0_COMPA_vect,
260 [AVR_TIMER_COMPB] = {
262 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
263 .com_pin = AVR_IO_REGBIT(PORTB, 4),
265 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
266 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
267 .vector = TIMER0_COMPB_vect,
274 .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
275 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
276 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
278 [0] = AVR_TIMER_WGM_NORMAL16(),
279 [1] = AVR_TIMER_WGM_FCPWM8(),
280 [2] = AVR_TIMER_WGM_FCPWM9(),
281 [3] = AVR_TIMER_WGM_FCPWM10(),
282 [4] = AVR_TIMER_WGM_CTC(),
283 [5] = AVR_TIMER_WGM_FASTPWM8(),
284 [6] = AVR_TIMER_WGM_FASTPWM9(),
285 [7] = AVR_TIMER_WGM_FASTPWM10(),
286 [12] = AVR_TIMER_WGM_ICCTC(),
287 [14] = AVR_TIMER_WGM_ICPWM(),
288 [15] = AVR_TIMER_WGM_OCPWM(),
290 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
291 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
298 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
299 .icp = AVR_IO_REGBIT(PORTD, 6),
302 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
303 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
304 .vector = TIMER1_OVF_vect,
307 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
308 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
309 .vector = TIMER1_CAPT_vect,
312 [AVR_TIMER_COMPA] = {
314 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
315 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
316 .com_pin = AVR_IO_REGBIT(PORTD, 5),
318 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
319 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
320 .vector = TIMER1_COMPA_vect,
323 [AVR_TIMER_COMPB] = {
326 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
327 .com_pin = AVR_IO_REGBIT(PORTD, 4),
329 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
330 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
331 .vector = TIMER1_COMPB_vect,
338 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
340 [0] = AVR_TIMER_WGM_NORMAL8(),
341 [2] = AVR_TIMER_WGM_CTC(),
342 [3] = AVR_TIMER_WGM_FASTPWM8(),
343 [7] = AVR_TIMER_WGM_OCPWM(),
345 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
346 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
350 // asynchronous timer source bit.. if set, use 32khz frequency
351 .as2 = AVR_IO_REGBIT(ASSR, AS2),
354 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
355 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
356 .vector = TIMER2_OVF_vect,
359 [AVR_TIMER_COMPA] = {
361 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
362 .com_pin = AVR_IO_REGBIT(PORTD, 7),
364 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
365 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
366 .vector = TIMER2_COMPA_vect,
369 [AVR_TIMER_COMPB] = {
371 .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
372 .com_pin = AVR_IO_REGBIT(PORTD, 6),
374 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
375 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
376 .vector = TIMER2_COMPB_vect,
382 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
388 .spe = AVR_IO_REGBIT(SPCR, SPE),
389 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
391 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
393 .enable = AVR_IO_REGBIT(SPCR, SPIE),
394 .raised = AVR_IO_REGBIT(SPSR, SPIF),
395 .vector = SPI_STC_vect,
400 .disabled = AVR_IO_REGBIT(PRR,PRTWI),
409 .twen = AVR_IO_REGBIT(TWCR, TWEN),
410 .twea = AVR_IO_REGBIT(TWCR, TWEA),
411 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
412 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
413 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
415 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
416 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
419 .enable = AVR_IO_REGBIT(TWCR, TWIE),
420 .raised = AVR_IO_REGBIT(TWCR, TWINT),
428 #endif /* SIM_CORENAME */
430 #endif /* __SIM_MEGAX4_H__ */