4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 #ifndef __SIM_MEGAX4_H__
23 #define __SIM_MEGAX4_H__
26 #include "sim_core_declare.h"
27 #include "avr_eeprom.h"
28 #include "avr_flash.h"
29 #include "avr_watchdog.h"
30 #include "avr_extint.h"
31 #include "avr_ioport.h"
34 #include "avr_timer.h"
38 void mx4_init(struct avr_t * avr);
39 void mx4_reset(struct avr_t * avr);
42 * This is a template for all of the x4 devices, hopefuly
48 avr_watchdog_t watchdog;
50 avr_ioport_t porta, portb, portc, portd;
51 avr_uart_t uart0,uart1;
53 avr_timer_t timer0,timer1,timer2;
61 #error SIM_MMCU is not declared
64 struct mcu_t SIM_CORENAME = {
72 AVR_EEPROM_DECLARE(EE_READY_vect),
73 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
74 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
76 AVR_EXTINT_DECLARE(0, 'D', PD2),
77 AVR_EXTINT_DECLARE(1, 'D', PD3),
78 AVR_EXTINT_DECLARE(2, 'B', PB3),
81 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
83 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
84 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
85 .vector = PCINT0_vect,
90 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
92 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
93 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
94 .vector = PCINT1_vect,
99 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
101 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
102 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
103 .vector = PCINT2_vect,
108 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
110 .enable = AVR_IO_REGBIT(PCICR, PCIE3),
111 .raised = AVR_IO_REGBIT(PCIFR, PCIF3),
112 .vector = PCINT3_vect,
118 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
122 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
123 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
131 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
132 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
133 .vector = USART0_RX_vect,
136 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
137 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
138 .vector = USART0_TX_vect,
141 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
142 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
143 .vector = USART0_UDRE_vect,
147 .disabled = AVR_IO_REGBIT(PRR,PRUSART1),
151 .txen = AVR_IO_REGBIT(UCSR1B, TXEN1),
152 .rxen = AVR_IO_REGBIT(UCSR1B, RXEN1),
160 .enable = AVR_IO_REGBIT(UCSR1B, RXCIE1),
161 .raised = AVR_IO_REGBIT(UCSR1A, RXC1),
162 .vector = USART1_RX_vect,
165 .enable = AVR_IO_REGBIT(UCSR1B, TXCIE1),
166 .raised = AVR_IO_REGBIT(UCSR1A, TXC1),
167 .vector = USART1_TX_vect,
170 .enable = AVR_IO_REGBIT(UCSR1B, UDRIE1),
171 .raised = AVR_IO_REGBIT(UCSR1A, UDRE1),
172 .vector = USART1_UDRE_vect,
177 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
178 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),
179 AVR_IO_REGBIT(ADMUX, MUX4),},
180 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
181 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
183 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
184 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
185 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
186 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
192 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
195 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
196 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
202 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
204 [0] = AVR_TIMER_WGM_NORMAL8(),
205 [2] = AVR_TIMER_WGM_CTC(),
206 [3] = AVR_TIMER_WGM_FASTPWM8(),
207 [7] = AVR_TIMER_WGM_OCPWM(),
209 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
210 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
215 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
216 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
217 .vector = TIMER0_OVF_vect,
220 [AVR_TIMER_COMPA] = {
222 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
223 .com_pin = AVR_IO_REGBIT(PORTB, 3),
225 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
226 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
227 .vector = TIMER0_COMPA_vect,
230 [AVR_TIMER_COMPB] = {
232 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
233 .com_pin = AVR_IO_REGBIT(PORTB, 4),
235 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
236 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
237 .vector = TIMER0_COMPB_vect,
244 .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
245 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
246 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
248 [0] = AVR_TIMER_WGM_NORMAL16(),
249 [4] = AVR_TIMER_WGM_CTC(),
250 [5] = AVR_TIMER_WGM_FASTPWM8(),
251 [6] = AVR_TIMER_WGM_FASTPWM9(),
252 [7] = AVR_TIMER_WGM_FASTPWM10(),
253 [12] = AVR_TIMER_WGM_ICCTC(),
254 [14] = AVR_TIMER_WGM_ICPWM(),
255 [15] = AVR_TIMER_WGM_OCPWM(),
257 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
258 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
266 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
267 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
268 .vector = TIMER1_OVF_vect,
271 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
272 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
273 .vector = TIMER1_CAPT_vect,
276 [AVR_TIMER_COMPA] = {
278 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
279 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
280 .com_pin = AVR_IO_REGBIT(PORTD, 5),
282 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
283 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
284 .vector = TIMER1_COMPA_vect,
287 [AVR_TIMER_COMPB] = {
290 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
291 .com_pin = AVR_IO_REGBIT(PORTD, 4),
293 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
294 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
295 .vector = TIMER1_COMPB_vect,
302 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
304 [0] = AVR_TIMER_WGM_NORMAL8(),
305 [2] = AVR_TIMER_WGM_CTC(),
306 [3] = AVR_TIMER_WGM_FASTPWM8(),
307 [7] = AVR_TIMER_WGM_OCPWM(),
309 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
310 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
314 // asynchronous timer source bit.. if set, use 32khz frequency
315 .as2 = AVR_IO_REGBIT(ASSR, AS2),
318 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
319 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
320 .vector = TIMER2_OVF_vect,
323 [AVR_TIMER_COMPA] = {
325 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
326 .com_pin = AVR_IO_REGBIT(PORTD, 7),
328 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
329 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
330 .vector = TIMER2_COMPA_vect,
333 [AVR_TIMER_COMPB] = {
335 .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
336 .com_pin = AVR_IO_REGBIT(PORTD, 6),
338 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
339 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
340 .vector = TIMER2_COMPB_vect,
346 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
352 .spe = AVR_IO_REGBIT(SPCR, SPE),
353 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
355 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
357 .enable = AVR_IO_REGBIT(SPCR, SPIE),
358 .raised = AVR_IO_REGBIT(SPSR, SPIF),
359 .vector = SPI_STC_vect,
364 .disabled = AVR_IO_REGBIT(PRR,PRTWI),
373 .twen = AVR_IO_REGBIT(TWCR, TWEN),
374 .twea = AVR_IO_REGBIT(TWCR, TWEA),
375 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
376 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
377 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
379 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
380 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
383 .enable = AVR_IO_REGBIT(TWCR, TWIE),
384 .raised = AVR_IO_REGBIT(TWSR, TWINT),
391 #endif /* SIM_CORENAME */
393 #endif /* __SIM_MEGAX4_H__ */