4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef __SIM_MEGAX8_H__
24 #define __SIM_MEGAX8_H__
26 #include "sim_core_declare.h"
27 #include "avr_eeprom.h"
28 #include "avr_flash.h"
29 #include "avr_watchdog.h"
30 #include "avr_extint.h"
31 #include "avr_ioport.h"
34 #include "avr_timer.h"
38 void mx8_init(struct avr_t * avr);
39 void mx8_reset(struct avr_t * avr);
42 * This is a template for all of the x8 devices, hopefully
47 avr_watchdog_t watchdog;
50 avr_ioport_t portb,portc,portd;
53 avr_timer_t timer0,timer1,timer2;
60 #ifndef SIM_VECTOR_SIZE
61 #error SIM_VECTOR_SIZE is not declared
64 #error SIM_MMCU is not declared
67 struct mcu_t SIM_CORENAME = {
70 DEFAULT_CORE(SIM_VECTOR_SIZE),
75 AVR_EEPROM_DECLARE(EE_READY_vect),
76 AVR_SELFPROG_DECLARE(SPMCSR, SELFPRGEN, SPM_READY_vect),
77 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
79 AVR_EXTINT_DECLARE(0, 'D', 2),
80 AVR_EXTINT_DECLARE(1, 'D', 3),
83 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
85 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
86 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
87 .vector = PCINT0_vect,
92 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
94 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
95 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
96 .vector = PCINT1_vect,
101 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
103 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
104 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
105 .vector = PCINT2_vect,
111 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
115 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
116 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
117 .usbs = AVR_IO_REGBIT(UCSR0C, USBS0),
118 .ucsz = AVR_IO_REGBITS(UCSR0C, UCSZ00, 0x3), // 2 bits
119 .ucsz2 = AVR_IO_REGBIT(UCSR0B, UCSZ02), // 1 bits
127 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
128 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
129 .vector = USART_RX_vect,
132 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
133 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
134 .vector = USART_TX_vect,
137 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
138 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
139 .vector = USART_UDRE_vect,
144 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
145 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
146 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
147 .ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V110, },
149 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
151 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
152 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
153 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
154 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
160 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
163 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
164 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
165 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
166 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_TEMP(),
167 [14] = AVR_ADC_REF(1100), // 1.1V
168 [15] = AVR_ADC_REF(0), // GND
171 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
172 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
178 .disabled = AVR_IO_REGBIT(PRR,PRTIM0),
179 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
181 [0] = AVR_TIMER_WGM_NORMAL8(),
182 [2] = AVR_TIMER_WGM_CTC(),
183 [3] = AVR_TIMER_WGM_FASTPWM8(),
184 [7] = AVR_TIMER_WGM_OCPWM(),
186 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
187 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
192 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
193 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
194 .vector = TIMER0_OVF_vect,
197 [AVR_TIMER_COMPA] = {
199 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
200 .com_pin = AVR_IO_REGBIT(PORTD, 6),
202 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
203 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
204 .vector = TIMER0_COMPA_vect,
207 [AVR_TIMER_COMPB] = {
209 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
210 .com_pin = AVR_IO_REGBIT(PORTD, 5),
212 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
213 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
214 .vector = TIMER0_COMPB_vect,
221 .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
222 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
223 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
225 [0] = AVR_TIMER_WGM_NORMAL16(),
226 [4] = AVR_TIMER_WGM_CTC(),
227 [5] = AVR_TIMER_WGM_FASTPWM8(),
228 [6] = AVR_TIMER_WGM_FASTPWM9(),
229 [7] = AVR_TIMER_WGM_FASTPWM10(),
230 [12] = AVR_TIMER_WGM_ICCTC(),
231 [14] = AVR_TIMER_WGM_ICPWM(),
232 [15] = AVR_TIMER_WGM_OCPWM(),
234 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
235 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
242 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
243 .icp = AVR_IO_REGBIT(PORTB, 0),
246 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
247 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
248 .vector = TIMER1_OVF_vect,
251 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
252 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
253 .vector = TIMER1_CAPT_vect,
256 [AVR_TIMER_COMPA] = {
258 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
259 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
260 .com_pin = AVR_IO_REGBIT(PORTB, 1),
262 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
263 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
264 .vector = TIMER1_COMPA_vect,
267 [AVR_TIMER_COMPB] = {
270 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
271 .com_pin = AVR_IO_REGBIT(PORTB, 2),
273 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
274 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
275 .vector = TIMER1_COMPB_vect,
282 .disabled = AVR_IO_REGBIT(PRR,PRTIM2),
283 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
285 [0] = AVR_TIMER_WGM_NORMAL8(),
286 [2] = AVR_TIMER_WGM_CTC(),
287 [3] = AVR_TIMER_WGM_FASTPWM8(),
288 [7] = AVR_TIMER_WGM_OCPWM(),
291 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
292 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
296 // asynchronous timer source bit.. if set, use 32khz frequency
297 .as2 = AVR_IO_REGBIT(ASSR, AS2),
300 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
301 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
302 .vector = TIMER2_OVF_vect,
305 [AVR_TIMER_COMPA] = {
307 .com = AVR_IO_REGBITS(TCCR2A, COM2A0, 0x3),
308 .com_pin = AVR_IO_REGBIT(PORTB, 3),
310 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
311 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
312 .vector = TIMER2_COMPA_vect,
315 [AVR_TIMER_COMPB] = {
317 .com = AVR_IO_REGBITS(TCCR2A, COM2B0, 0x3),
318 .com_pin = AVR_IO_REGBIT(PORTD, 3),
320 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
321 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
322 .vector = TIMER2_COMPB_vect,
328 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
334 .spe = AVR_IO_REGBIT(SPCR, SPE),
335 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
337 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
339 .enable = AVR_IO_REGBIT(SPCR, SPIE),
340 .raised = AVR_IO_REGBIT(SPSR, SPIF),
341 .vector = SPI_STC_vect,
346 .disabled = AVR_IO_REGBIT(PRR,PRTWI),
355 .twen = AVR_IO_REGBIT(TWCR, TWEN),
356 .twea = AVR_IO_REGBIT(TWCR, TWEA),
357 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
358 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
359 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
361 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
362 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
365 .enable = AVR_IO_REGBIT(TWCR, TWIE),
366 .raised = AVR_IO_REGBIT(TWCR, TWINT),
372 #endif /* SIM_CORENAME */
374 #endif /* __SIM_MEGAX8_H__ */