4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef __SIM_MEGAX8_H__
24 #define __SIM_MEGAX8_H__
26 #include "sim_core_declare.h"
27 #include "avr_eeprom.h"
28 #include "avr_extint.h"
29 #include "avr_ioport.h"
31 #include "avr_timer8.h"
35 void mx8_init(struct avr_t * avr);
36 void mx8_reset(struct avr_t * avr);
39 * This is a template for all of the x8 devices, hopefuly
45 avr_ioport_t portb,portc,portd;
47 avr_timer8_t timer0,timer2;
54 #ifndef SIM_VECTOR_SIZE
55 #error SIM_VECTOR_SIZE is not declared
58 #error SIM_MMCU is not declared
61 struct mcu_t SIM_CORENAME = {
64 DEFAULT_CORE(SIM_VECTOR_SIZE),
69 AVR_EEPROM_DECLARE(EE_READY_vect),
71 AVR_EXTINT_DECLARE(0, 'D', PD2),
72 AVR_EXTINT_DECLARE(1, 'D', PD3),
75 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
77 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
78 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
79 .vector = PCINT0_vect,
84 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
86 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
87 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
88 .vector = PCINT1_vect,
93 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
95 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
96 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
97 .vector = PCINT2_vect,
103 .disabled = AVR_IO_REGBIT(PRR,PRUSART0),
107 .txen = AVR_IO_REGBIT(UCSR0B, TXEN0),
108 .rxen = AVR_IO_REGBIT(UCSR0B, RXEN0),
116 .enable = AVR_IO_REGBIT(UCSR0B, RXCIE0),
117 .raised = AVR_IO_REGBIT(UCSR0A, RXC0),
118 .vector = USART_RX_vect,
121 .enable = AVR_IO_REGBIT(UCSR0B, TXCIE0),
122 .raised = AVR_IO_REGBIT(UCSR0A, TXC0),
123 .vector = USART_TX_vect,
126 .enable = AVR_IO_REGBIT(UCSR0B, UDRIE0),
127 .raised = AVR_IO_REGBIT(UCSR0A, UDRE0),
128 .vector = USART_UDRE_vect,
134 .disabled = AVR_IO_REGBIT(PRR,PRTIM0),
135 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
136 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
137 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
144 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
145 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
146 .vector = TIMER0_OVF_vect,
149 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
150 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
151 .vector = TIMER0_COMPA_vect,
154 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
155 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
156 .vector = TIMER0_COMPB_vect,
161 .disabled = AVR_IO_REGBIT(PRR,PRTIM2),
162 .wgm = { AVR_IO_REGBIT(TCCR2A, WGM20), AVR_IO_REGBIT(TCCR2A, WGM21), AVR_IO_REGBIT(TCCR2B, WGM22) },
163 .cs = { AVR_IO_REGBIT(TCCR2B, CS20), AVR_IO_REGBIT(TCCR2B, CS21), AVR_IO_REGBIT(TCCR2B, CS22) },
164 .cs_div = { 0, 0, 3 /* 8 */, 5 /* 32 */, 6 /* 64 */, 7 /* 128 */, 8 /* 256 */, 10 /* 1024 */ },
170 // asynchronous timer source bit.. if set, use 32khz frequency
171 .as2 = AVR_IO_REGBIT(ASSR, AS2),
174 .enable = AVR_IO_REGBIT(TIMSK2, TOIE2),
175 .raised = AVR_IO_REGBIT(TIFR2, TOV2),
176 .vector = TIMER2_OVF_vect,
179 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2A),
180 .raised = AVR_IO_REGBIT(TIFR2, OCF2A),
181 .vector = TIMER2_COMPA_vect,
184 .enable = AVR_IO_REGBIT(TIMSK2, OCIE2B),
185 .raised = AVR_IO_REGBIT(TIFR2, OCF2B),
186 .vector = TIMER2_COMPB_vect,
191 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
197 .spe = AVR_IO_REGBIT(SPCR, SPE),
198 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
200 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
202 .enable = AVR_IO_REGBIT(SPCR, SPIE),
203 .raised = AVR_IO_REGBIT(SPSR, SPIF),
204 .vector = SPI_STC_vect,
209 .disabled = AVR_IO_REGBIT(PRR,PRTWI),
218 .twen = AVR_IO_REGBIT(TWCR, TWEN),
219 .twea = AVR_IO_REGBIT(TWCR, TWEA),
220 .twsta = AVR_IO_REGBIT(TWCR, TWSTA),
221 .twsto = AVR_IO_REGBIT(TWCR, TWSTO),
222 .twwc = AVR_IO_REGBIT(TWCR, TWWC),
224 .twsr = AVR_IO_REGBITS(TWSR, TWS3, 0x1f), // 5 bits
225 .twps = AVR_IO_REGBITS(TWSR, TWPS0, 0x3), // 2 bits
228 .enable = AVR_IO_REGBIT(TWCR, TWIE),
229 .raised = AVR_IO_REGBIT(TWSR, TWINT),
235 #endif /* SIM_CORENAME */
237 #endif /* __SIM_MEGAX8_H__ */