4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
23 #ifndef __SIM_MEGAX8_H__
24 #define __SIM_MEGAX8_H__
26 #include "sim_core_declare.h"
27 #include "avr_eeprom.h"
28 #include "avr_flash.h"
29 #include "avr_watchdog.h"
30 #include "avr_extint.h"
31 #include "avr_ioport.h"
35 #include "avr_timer.h"
38 void mxm1_init(struct avr_t * avr);
39 void mxm1_reset(struct avr_t * avr);
42 * This is a template for all of the xm1 devices, hopefully
47 avr_watchdog_t watchdog;
50 avr_ioport_t portb,portc,portd,porte;
53 avr_timer_t timer0,timer1;
59 #ifndef SIM_VECTOR_SIZE
60 #error SIM_VECTOR_SIZE is not declared
63 #error SIM_MMCU is not declared
66 struct mcu_t SIM_CORENAME = {
69 DEFAULT_CORE(SIM_VECTOR_SIZE),
74 AVR_EEPROM_DECLARE_NOEEPM(EE_READY_vect),
75 AVR_SELFPROG_DECLARE(SPMCSR, SPMEN, SPM_READY_vect),
76 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
78 AVR_EXTINT_DECLARE(0, 'D', 6),
79 AVR_EXTINT_DECLARE(1, 'B', 2),
80 AVR_EXTINT_DECLARE(2, 'B', 5),
81 AVR_EXTINT_DECLARE(3, 'C', 0),
84 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
86 .enable = AVR_IO_REGBIT(PCICR, PCIE0),
87 .raised = AVR_IO_REGBIT(PCIFR, PCIF0),
88 .vector = PCINT0_vect,
93 .name = 'C', .r_port = PORTC, .r_ddr = DDRC, .r_pin = PINC,
95 .enable = AVR_IO_REGBIT(PCICR, PCIE1),
96 .raised = AVR_IO_REGBIT(PCIFR, PCIF1),
97 .vector = PCINT1_vect,
102 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
104 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
105 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
106 .vector = PCINT2_vect,
111 .name = 'E', .r_port = PORTE, .r_ddr = DDRE, .r_pin = PINE,
113 .enable = AVR_IO_REGBIT(PCICR, PCIE2),
114 .raised = AVR_IO_REGBIT(PCIFR, PCIF2),
115 .vector = PCINT2_vect,
122 .r_linbrrh = LINBRRH,
123 .r_linbrrl = LINBRRL,
125 .lena = AVR_IO_REGBIT( LINCR, LENA),
126 .ldisr = AVR_IO_REGBIT( LINBTR, LDISR),
127 .lbt = AVR_IO_REGBITS( LINBTR, LBT0, 0x3F), // 5 bits
133 .txen = AVR_IO_REGBIT(LINCR, LCMD0),
134 .rxen = AVR_IO_REGBIT(LINCR, LCMD1),
136 // note that control and BAUD calculation is handled via LIN regs above
144 .enable = AVR_IO_REGBIT(LINENIR, LENRXOK),
145 .raised = AVR_IO_REGBIT(LINSIR, LRXOK),
146 .vector = LIN_TC_vect,
149 .enable = AVR_IO_REGBIT(LINENIR, LENTXOK),
150 .raised = AVR_IO_REGBIT(LINSIR, LTXOK),
151 .vector = LIN_TC_vect,
153 /* .udrc doesn't exist in the LIN UART */
158 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
159 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),AVR_IO_REGBIT(ADMUX, MUX4)},
160 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1)},
161 .ref_values = { [1] = ADC_VREF_AVCC, [3] = ADC_VREF_V256, },
163 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
165 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
166 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
167 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
168 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
174 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
177 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
178 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
179 [4] = AVR_ADC_SINGLE(4), [5] = AVR_ADC_SINGLE(5),
180 [6] = AVR_ADC_SINGLE(6), [7] = AVR_ADC_SINGLE(7),
181 [8] = AVR_ADC_SINGLE(8), [9] = AVR_ADC_SINGLE(9),
182 [10] = AVR_ADC_SINGLE(10), [11] = AVR_ADC_TEMP(),
183 // AMP0/1/2 is missing, no clue what to do ...
184 [17] = AVR_ADC_REF(2560), // 1.1V
185 [18] = AVR_ADC_REF(0), // GND
188 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
189 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
195 .disabled = AVR_IO_REGBIT(PRR,PRTIM0),
196 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
198 [0] = AVR_TIMER_WGM_NORMAL8(),
199 [2] = AVR_TIMER_WGM_CTC(),
200 [3] = AVR_TIMER_WGM_FASTPWM8(),
201 [7] = AVR_TIMER_WGM_OCPWM(),
203 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
204 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
209 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
210 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
211 .vector = TIMER0_OVF_vect,
214 [AVR_TIMER_COMPA] = {
216 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
217 .com_pin = AVR_IO_REGBIT(PORTD, 3),
219 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
220 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
221 .vector = TIMER0_COMPA_vect,
224 [AVR_TIMER_COMPB] = {
226 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
227 .com_pin = AVR_IO_REGBIT(PORTE, 1),
229 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
230 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
231 .vector = TIMER0_COMPB_vect,
238 .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
239 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
240 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
242 [0] = AVR_TIMER_WGM_NORMAL16(),
243 [4] = AVR_TIMER_WGM_CTC(),
244 [5] = AVR_TIMER_WGM_FASTPWM8(),
245 [6] = AVR_TIMER_WGM_FASTPWM9(),
246 [7] = AVR_TIMER_WGM_FASTPWM10(),
247 [12] = AVR_TIMER_WGM_ICCTC(),
248 [14] = AVR_TIMER_WGM_ICPWM(),
249 [15] = AVR_TIMER_WGM_OCPWM(),
251 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
252 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
259 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
260 .icp = AVR_IO_REGBIT(PORTD, 4), // default port for ICP1 (A)
263 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
264 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
265 .vector = TIMER1_OVF_vect,
268 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
269 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
270 .vector = TIMER1_CAPT_vect,
273 [AVR_TIMER_COMPA] = {
275 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
276 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
277 .com_pin = AVR_IO_REGBIT(PORTD, 2),
279 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
280 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
281 .vector = TIMER1_COMPA_vect,
284 [AVR_TIMER_COMPB] = {
287 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
288 .com_pin = AVR_IO_REGBIT(PORTC, 1),
290 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
291 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
292 .vector = TIMER1_COMPB_vect,
298 .disabled = AVR_IO_REGBIT(PRR,PRSPI),
304 .spe = AVR_IO_REGBIT(SPCR, SPE),
305 .mstr = AVR_IO_REGBIT(SPCR, MSTR),
307 .spr = { AVR_IO_REGBIT(SPCR, SPR0), AVR_IO_REGBIT(SPCR, SPR1), AVR_IO_REGBIT(SPSR, SPI2X) },
309 .enable = AVR_IO_REGBIT(SPCR, SPIE),
310 .raised = AVR_IO_REGBIT(SPSR, SPIF),
311 .vector = SPI_STC_vect,
316 #endif /* SIM_CORENAME */
318 #endif /* __SIM_MEGAX8_H__ */