4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 #include "sim_core_declare.h"
23 #include "avr_eeprom.h"
24 #include "avr_watchdog.h"
25 #include "avr_extint.h"
26 #include "avr_ioport.h"
28 #include "avr_timer.h"
30 static void init(struct avr_t * avr);
31 static void reset(struct avr_t * avr);
35 #include "avr/iotn2313.h"
38 * This is a template for all of the tinyx5 devices, hopefully
40 static const struct mcu_t {
43 avr_watchdog_t watchdog;
45 avr_ioport_t porta, portb, portd;
47 avr_timer_t timer0,timer1;
56 AVR_EEPROM_DECLARE_8BIT(EEPROM_READY_vect),
57 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_OVERFLOW_vect),
59 AVR_EXTINT_TINY_DECLARE(0, 'D', 2, EIFR),
60 AVR_EXTINT_TINY_DECLARE(1, 'D', 3, EIFR),
62 .porta = { // port A has no PCInts..
63 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
66 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
68 .enable = AVR_IO_REGBIT(GIMSK, PCIE),
69 .raised = AVR_IO_REGBIT(EIFR, PCIF),
74 .portd = { // port D has no PCInts..
75 .name = 'D', .r_port = PORTD, .r_ddr = DDRD, .r_pin = PIND,
78 // no PRR register on the 2313
79 //.disabled = AVR_IO_REGBIT(PRR,PRUSART0),
83 .txen = AVR_IO_REGBIT(UCSRB, TXEN),
84 .rxen = AVR_IO_REGBIT(UCSRB, RXEN),
85 .ucsz = AVR_IO_REGBITS(UCSRC, UCSZ0, 0x3), // 2 bits
86 .ucsz2 = AVR_IO_REGBIT(UCSRB, UCSZ2), // 1 bits
94 .enable = AVR_IO_REGBIT(UCSRB, RXCIE),
95 .raised = AVR_IO_REGBIT(UCSRA, RXC),
96 .vector = USART_RX_vect,
99 .enable = AVR_IO_REGBIT(UCSRB, TXCIE),
100 .raised = AVR_IO_REGBIT(UCSRA, TXC),
101 .vector = USART_TX_vect,
104 .enable = AVR_IO_REGBIT(UCSRB, UDRIE),
105 .raised = AVR_IO_REGBIT(UCSRA, UDRE),
106 .vector = USART_UDRE_vect,
111 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
113 [0] = AVR_TIMER_WGM_NORMAL8(),
114 [2] = AVR_TIMER_WGM_CTC(),
115 [3] = AVR_TIMER_WGM_FASTPWM8(),
116 [7] = AVR_TIMER_WGM_OCPWM(),
118 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
119 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
124 .enable = AVR_IO_REGBIT(TIMSK, TOIE0),
125 .raised = AVR_IO_REGBIT(TIFR, TOV0),
126 .vector = TIMER0_OVF_vect,
129 [AVR_TIMER_COMPA] = {
131 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
132 .com_pin = AVR_IO_REGBIT(PORTB, 2),
134 .enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
135 .raised = AVR_IO_REGBIT(TIFR, OCF0A),
136 .vector = TIMER0_COMPA_vect,
139 [AVR_TIMER_COMPB] = {
141 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
142 .com_pin = AVR_IO_REGBIT(PORTD, 5),
144 .enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
145 .raised = AVR_IO_REGBIT(TIFR, OCF0B),
146 .vector = TIMER0_COMPB_vect,
153 // .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
154 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
155 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
157 [0] = AVR_TIMER_WGM_NORMAL16(),
158 [4] = AVR_TIMER_WGM_CTC(),
159 [5] = AVR_TIMER_WGM_FASTPWM8(),
160 [6] = AVR_TIMER_WGM_FASTPWM9(),
161 [7] = AVR_TIMER_WGM_FASTPWM10(),
162 [12] = AVR_TIMER_WGM_ICCTC(),
163 [14] = AVR_TIMER_WGM_ICPWM(),
164 [15] = AVR_TIMER_WGM_OCPWM(),
166 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
167 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
174 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
175 .icp = AVR_IO_REGBIT(PORTD, 6),
178 .enable = AVR_IO_REGBIT(TIMSK, TOIE1),
179 .raised = AVR_IO_REGBIT(TIFR, TOV1),
180 .vector = TIMER1_OVF_vect,
183 .enable = AVR_IO_REGBIT(TIMSK, ICIE1),
184 .raised = AVR_IO_REGBIT(TIFR, ICF1),
185 .vector = TIMER1_CAPT_vect,
188 [AVR_TIMER_COMPA] = {
190 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
191 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
192 .com_pin = AVR_IO_REGBIT(PORTB, 3),
194 .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
195 .raised = AVR_IO_REGBIT(TIFR, OCF1A),
196 .vector = TIMER1_COMPA_vect,
199 [AVR_TIMER_COMPB] = {
202 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
203 .com_pin = AVR_IO_REGBIT(PORTB, 4),
205 .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
206 .raised = AVR_IO_REGBIT(TIFR, OCF1B),
207 .vector = TIMER1_COMPB_vect,
214 static avr_t * make()
216 return avr_core_allocate(&mcu.core, sizeof(struct mcu_t));
219 avr_kind_t tiny2313 = {
220 .names = { "attiny2313", "attiny2313v" },
224 static void init(struct avr_t * avr)
226 struct mcu_t * mcu = (struct mcu_t*)avr;
228 avr_eeprom_init(avr, &mcu->eeprom);
229 avr_watchdog_init(avr, &mcu->watchdog);
230 avr_extint_init(avr, &mcu->extint);
231 avr_ioport_init(avr, &mcu->porta);
232 avr_ioport_init(avr, &mcu->portb);
233 avr_ioport_init(avr, &mcu->portd);
234 avr_uart_init(avr, &mcu->uart);
235 avr_timer_init(avr, &mcu->timer0);
236 avr_timer_init(avr, &mcu->timer1);
239 static void reset(struct avr_t * avr)
241 // struct mcu_t * mcu = (struct mcu_t*)avr;