4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
5 Jon Escombe <lists@dresco.co.uk>
7 This file is part of simavr.
9 simavr is free software: you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation, either version 3 of the License, or
12 (at your option) any later version.
14 simavr is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 #ifndef __SIM_TINYX4_H__
25 #define __SIM_TINYX4_H__
27 #include "sim_core_declare.h"
28 #include "avr_eeprom.h"
29 #include "avr_watchdog.h"
30 #include "avr_extint.h"
31 #include "avr_ioport.h"
33 #include "avr_timer.h"
35 void tx4_init(struct avr_t * avr);
36 void tx4_reset(struct avr_t * avr);
39 * This is a template for all of the tinyx4 devices, hopefully
44 avr_watchdog_t watchdog;
46 avr_ioport_t porta, portb;
48 avr_timer_t timer0, timer1;
53 #ifndef SIM_VECTOR_SIZE
54 #error SIM_VECTOR_SIZE is not declared
57 #error SIM_MMCU is not declared
60 const struct mcu_t SIM_CORENAME = {
63 DEFAULT_CORE(SIM_VECTOR_SIZE),
68 AVR_EEPROM_DECLARE(EE_RDY_vect),
69 AVR_WATCHDOG_DECLARE(WDTCSR, WDT_vect),
71 AVR_EXTINT_TINY_DECLARE(0, 'B', PB2, GIFR),
74 .name = 'A', .r_port = PORTA, .r_ddr = DDRA, .r_pin = PINA,
76 .enable = AVR_IO_REGBIT(GIMSK, PCIE0),
77 .raised = AVR_IO_REGBIT(GIFR, PCIF0),
78 .vector = PCINT0_vect,
83 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
85 .enable = AVR_IO_REGBIT(GIMSK, PCIE1),
86 .raised = AVR_IO_REGBIT(GIFR, PCIF1),
87 .vector = PCINT1_vect,
93 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
94 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
95 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1), },
97 [0] = ADC_VREF_VCC, [1] = ADC_VREF_AVCC,
101 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
103 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
104 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
105 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
106 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
112 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
113 .bin = AVR_IO_REGBIT(ADCSRB, BIN),
116 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
117 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
119 [ 4] = AVR_ADC_DIFF(2, 2, 1), [ 5] = AVR_ADC_DIFF(2, 2, 20),
120 [ 6] = AVR_ADC_DIFF(2, 3, 1), [ 7] = AVR_ADC_DIFF(2, 3, 20),
121 [ 8] = AVR_ADC_DIFF(0, 0, 1), [ 9] = AVR_ADC_DIFF(0, 0, 20),
122 [10] = AVR_ADC_DIFF(0, 1, 1), [11] = AVR_ADC_DIFF(0, 1, 20),
123 [12] = AVR_ADC_REF(1100), // Vbg
124 [13] = AVR_ADC_REF(0), // GND
125 [15] = AVR_ADC_TEMP(),
129 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
130 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
136 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
138 [0] = AVR_TIMER_WGM_NORMAL8(),
139 [2] = AVR_TIMER_WGM_CTC(),
140 [3] = AVR_TIMER_WGM_FASTPWM8(),
141 [7] = AVR_TIMER_WGM_OCPWM(),
143 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
144 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
149 .enable = AVR_IO_REGBIT(TIMSK0, TOIE0),
150 .raised = AVR_IO_REGBIT(TIFR0, TOV0),
151 .vector = TIM0_OVF_vect,
154 [AVR_TIMER_COMPA] = {
156 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
157 .com_pin = AVR_IO_REGBIT(PORTB, 0),
159 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0A),
160 .raised = AVR_IO_REGBIT(TIFR0, OCF0A),
161 .vector = TIM0_COMPA_vect,
164 [AVR_TIMER_COMPB] = {
166 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
167 .com_pin = AVR_IO_REGBIT(PORTB, 1),
169 .enable = AVR_IO_REGBIT(TIMSK0, OCIE0B),
170 .raised = AVR_IO_REGBIT(TIFR0, OCF0B),
171 .vector = TIM0_COMPB_vect,
178 .disabled = AVR_IO_REGBIT(PRR,PRTIM1),
179 .wgm = { AVR_IO_REGBIT(TCCR1A, WGM10), AVR_IO_REGBIT(TCCR1A, WGM11),
180 AVR_IO_REGBIT(TCCR1B, WGM12), AVR_IO_REGBIT(TCCR1B, WGM13) },
182 [0] = AVR_TIMER_WGM_NORMAL16(),
183 [4] = AVR_TIMER_WGM_CTC(),
184 [5] = AVR_TIMER_WGM_FASTPWM8(),
185 [6] = AVR_TIMER_WGM_FASTPWM9(),
186 [7] = AVR_TIMER_WGM_FASTPWM10(),
187 [12] = AVR_TIMER_WGM_ICCTC(),
188 [14] = AVR_TIMER_WGM_ICPWM(),
189 [15] = AVR_TIMER_WGM_OCPWM(),
191 .cs = { AVR_IO_REGBIT(TCCR1B, CS10), AVR_IO_REGBIT(TCCR1B, CS11), AVR_IO_REGBIT(TCCR1B, CS12) },
192 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ /* External clock T1 is not handled */},
199 .ices = AVR_IO_REGBIT(TCCR1B, ICES1),
200 .icp = AVR_IO_REGBIT(PORTB, 0),
203 .enable = AVR_IO_REGBIT(TIMSK1, TOIE1),
204 .raised = AVR_IO_REGBIT(TIFR1, TOV1),
205 .vector = TIM1_OVF_vect,
208 .enable = AVR_IO_REGBIT(TIMSK1, ICIE1),
209 .raised = AVR_IO_REGBIT(TIFR1, ICF1),
210 .vector = TIM1_CAPT_vect,
213 [AVR_TIMER_COMPA] = {
215 .r_ocrh = OCR1AH, // 16 bits timers have two bytes of it
216 .com = AVR_IO_REGBITS(TCCR1A, COM1A0, 0x3),
217 .com_pin = AVR_IO_REGBIT(PORTB, 1),
219 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1A),
220 .raised = AVR_IO_REGBIT(TIFR1, OCF1A),
221 .vector = TIM1_COMPA_vect,
224 [AVR_TIMER_COMPB] = {
227 .com = AVR_IO_REGBITS(TCCR1A, COM1B0, 0x3),
228 .com_pin = AVR_IO_REGBIT(PORTB, 2),
230 .enable = AVR_IO_REGBIT(TIMSK1, OCIE1B),
231 .raised = AVR_IO_REGBIT(TIFR1, OCF1B),
232 .vector = TIM1_COMPB_vect,
238 #endif /* SIM_CORENAME */
240 #endif /* __SIM_TINYX4_H__ */