4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
5 Jon Escombe <lists@dresco.co.uk>
7 This file is part of simavr.
9 simavr is free software: you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation, either version 3 of the License, or
12 (at your option) any later version.
14 simavr is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 #ifndef __SIM_TINYX5_H__
25 #define __SIM_TINYX5_H__
27 #include "sim_core_declare.h"
28 #include "avr_eeprom.h"
29 #include "avr_watchdog.h"
30 #include "avr_extint.h"
31 #include "avr_ioport.h"
33 #include "avr_timer.h"
35 void tx5_init(struct avr_t * avr);
36 void tx5_reset(struct avr_t * avr);
39 * This is a template for all of the tinyx5 devices, hopefully
44 avr_watchdog_t watchdog;
48 avr_timer_t timer0, timer1;
53 #ifndef SIM_VECTOR_SIZE
54 #error SIM_VECTOR_SIZE is not declared
57 #error SIM_MMCU is not declared
60 const struct mcu_t SIM_CORENAME = {
63 DEFAULT_CORE(SIM_VECTOR_SIZE),
68 AVR_EEPROM_DECLARE(EE_RDY_vect),
69 AVR_WATCHDOG_DECLARE(WDTCR, WDT_vect),
71 AVR_EXTINT_TINY_DECLARE(0, 'B', PB2, GIFR),
74 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
76 .enable = AVR_IO_REGBIT(GIMSK, PCIE),
77 .raised = AVR_IO_REGBIT(GIFR, PCIF),
78 .vector = PCINT0_vect,
84 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
85 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
86 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1), AVR_IO_REGBIT(ADMUX, REFS2), },
88 [0] = ADC_VREF_VCC, [1] = ADC_VREF_AVCC,
89 [2] = ADC_VREF_V110, [5] = ADC_VREF_V256,
93 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
95 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
96 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
97 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
98 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
104 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
105 .bin = AVR_IO_REGBIT(ADCSRB, BIN),
106 .ipr = AVR_IO_REGBIT(ADCSRA, IPR),
109 [0] = AVR_ADC_SINGLE(0), [1] = AVR_ADC_SINGLE(1),
110 [2] = AVR_ADC_SINGLE(2), [3] = AVR_ADC_SINGLE(3),
112 [ 4] = AVR_ADC_DIFF(2, 2, 1), [ 5] = AVR_ADC_DIFF(2, 2, 20),
113 [ 6] = AVR_ADC_DIFF(2, 3, 1), [ 7] = AVR_ADC_DIFF(2, 3, 20),
114 [ 8] = AVR_ADC_DIFF(0, 0, 1), [ 9] = AVR_ADC_DIFF(0, 0, 20),
115 [10] = AVR_ADC_DIFF(0, 1, 1), [11] = AVR_ADC_DIFF(0, 1, 20),
116 [12] = AVR_ADC_REF(1100), // Vbg
117 [13] = AVR_ADC_REF(0), // GND
118 [15] = AVR_ADC_TEMP(),
122 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
123 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
129 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
131 [0] = AVR_TIMER_WGM_NORMAL8(),
132 [2] = AVR_TIMER_WGM_CTC(),
133 [3] = AVR_TIMER_WGM_FASTPWM8(),
134 [7] = AVR_TIMER_WGM_OCPWM(),
136 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
137 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
142 .enable = AVR_IO_REGBIT(TIMSK, TOIE0),
143 .raised = AVR_IO_REGBIT(TIFR, TOV0),
144 .vector = TIMER0_OVF_vect,
147 [AVR_TIMER_COMPA] = {
149 .com = AVR_IO_REGBITS(TCCR0A, COM0A0, 0x3),
150 .com_pin = AVR_IO_REGBIT(PORTB, 0),
152 .enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
153 .raised = AVR_IO_REGBIT(TIFR, OCF0A),
154 .vector = TIMER0_COMPA_vect,
157 [AVR_TIMER_COMPB] = {
159 .com = AVR_IO_REGBITS(TCCR0A, COM0B0, 0x3),
160 .com_pin = AVR_IO_REGBIT(PORTB, 1),
162 .enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
163 .raised = AVR_IO_REGBIT(TIFR, OCF0B),
164 .vector = TIMER0_COMPB_vect,
172 .cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) },
173 .cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ },
178 .enable = AVR_IO_REGBIT(TIMSK, TOIE1),
179 .raised = AVR_IO_REGBIT(TIFR, TOV1),
180 .vector = TIMER1_OVF_vect,
183 [AVR_TIMER_COMPA] = {
185 .com = AVR_IO_REGBITS(TCCR1, COM1A0, 0x3),
186 .com_pin = AVR_IO_REGBIT(PORTB, 1),
188 .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
189 .raised = AVR_IO_REGBIT(TIFR, OCF1A),
190 .vector = TIMER1_COMPA_vect,
193 [AVR_TIMER_COMPB] = {
195 .com = AVR_IO_REGBITS(GTCCR, COM1B0, 0x3),
196 .com_pin = AVR_IO_REGBIT(PORTB, 4),
198 .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
199 .raised = AVR_IO_REGBIT(TIFR, OCF1B),
200 .vector = TIMER1_COMPB_vect,
203 [AVR_TIMER_COMPC] = {
209 #endif /* SIM_CORENAME */
211 #endif /* __SIM_TINYX5_H__ */