4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
5 Jon Escombe <lists@dresco.co.uk>
7 This file is part of simavr.
9 simavr is free software: you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation, either version 3 of the License, or
12 (at your option) any later version.
14 simavr is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 #ifndef __SIM_TINYX5_H__
25 #define __SIM_TINYX5_H__
27 #include "sim_core_declare.h"
28 #include "avr_eeprom.h"
29 #include "avr_extint.h"
30 #include "avr_ioport.h"
32 #include "avr_timer.h"
34 void tx5_init(struct avr_t * avr);
35 void tx5_reset(struct avr_t * avr);
38 * This is a template for all of the tinyx5 devices, hopefully
46 avr_timer_t timer0, timer1;
51 #ifndef SIM_VECTOR_SIZE
52 #error SIM_VECTOR_SIZE is not declared
55 #error SIM_MMCU is not declared
58 struct mcu_t SIM_CORENAME = {
61 DEFAULT_CORE(SIM_VECTOR_SIZE),
66 AVR_EEPROM_DECLARE(EE_RDY_vect),
68 AVR_EXTINT_TINY_DECLARE(0, 'B', PB2, GIFR),
71 .name = 'B', .r_port = PORTB, .r_ddr = DDRB, .r_pin = PINB,
73 .enable = AVR_IO_REGBIT(GIMSK, PCIE),
74 .raised = AVR_IO_REGBIT(GIFR, PCIF),
75 .vector = PCINT0_vect,
81 .mux = { AVR_IO_REGBIT(ADMUX, MUX0), AVR_IO_REGBIT(ADMUX, MUX1),
82 AVR_IO_REGBIT(ADMUX, MUX2), AVR_IO_REGBIT(ADMUX, MUX3),},
83 .ref = { AVR_IO_REGBIT(ADMUX, REFS0), AVR_IO_REGBIT(ADMUX, REFS1), AVR_IO_REGBIT(ADMUX, REFS2), },
84 .adlar = AVR_IO_REGBIT(ADMUX, ADLAR),
86 .aden = AVR_IO_REGBIT(ADCSRA, ADEN),
87 .adsc = AVR_IO_REGBIT(ADCSRA, ADSC),
88 .adate = AVR_IO_REGBIT(ADCSRA, ADATE),
89 .adps = { AVR_IO_REGBIT(ADCSRA, ADPS0), AVR_IO_REGBIT(ADCSRA, ADPS1), AVR_IO_REGBIT(ADCSRA, ADPS2),},
95 .adts = { AVR_IO_REGBIT(ADCSRB, ADTS0), AVR_IO_REGBIT(ADCSRB, ADTS1), AVR_IO_REGBIT(ADCSRB, ADTS2),},
96 .bin = AVR_IO_REGBIT(ADCSRB, BIN),
97 .ipr = AVR_IO_REGBIT(ADCSRA, IPR),
100 .enable = AVR_IO_REGBIT(ADCSRA, ADIE),
101 .raised = AVR_IO_REGBIT(ADCSRA, ADIF),
107 .wgm = { AVR_IO_REGBIT(TCCR0A, WGM00), AVR_IO_REGBIT(TCCR0A, WGM01), AVR_IO_REGBIT(TCCR0B, WGM02) },
109 [0] = AVR_TIMER_WGM_NORMAL8(),
110 [2] = AVR_TIMER_WGM_CTC(),
111 [3] = AVR_TIMER_WGM_FASTPWM(),
112 [7] = AVR_TIMER_WGM_FASTPWM(),
114 .cs = { AVR_IO_REGBIT(TCCR0B, CS00), AVR_IO_REGBIT(TCCR0B, CS01), AVR_IO_REGBIT(TCCR0B, CS02) },
115 .cs_div = { 0, 0, 3 /* 8 */, 6 /* 64 */, 8 /* 256 */, 10 /* 1024 */ },
122 .enable = AVR_IO_REGBIT(TIMSK, TOIE0),
123 .raised = AVR_IO_REGBIT(TIFR, TOV0),
124 .vector = TIMER0_OVF_vect,
127 .enable = AVR_IO_REGBIT(TIMSK, OCIE0A),
128 .raised = AVR_IO_REGBIT(TIFR, OCF0A),
129 .vector = TIMER0_COMPA_vect,
132 .enable = AVR_IO_REGBIT(TIMSK, OCIE0B),
133 .raised = AVR_IO_REGBIT(TIFR, OCF0B),
134 .vector = TIMER0_COMPB_vect,
140 .cs = { AVR_IO_REGBIT(TCCR1, CS10), AVR_IO_REGBIT(TCCR1, CS11), AVR_IO_REGBIT(TCCR1, CS12), AVR_IO_REGBIT(TCCR1, CS13) },
141 .cs_div = { 0, 0, 1 /* 2 */, 2 /* 4 */, 3 /* 8 */, 4 /* 16 */ },
149 .enable = AVR_IO_REGBIT(TIMSK, TOIE1),
150 .raised = AVR_IO_REGBIT(TIFR, TOV1),
151 .vector = TIMER1_OVF_vect,
154 .enable = AVR_IO_REGBIT(TIMSK, OCIE1A),
155 .raised = AVR_IO_REGBIT(TIFR, OCF1A),
156 .vector = TIMER1_COMPA_vect,
159 .enable = AVR_IO_REGBIT(TIMSK, OCIE1B),
160 .raised = AVR_IO_REGBIT(TIFR, OCF1B),
161 .vector = TIMER1_COMPB_vect,
167 #endif /* SIM_CORENAME */
169 #endif /* __SIM_TINYX5_H__ */