4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
5 2011 Stephan Veigl <veig@gmx.net>
7 This file is part of simavr.
9 simavr is free software: you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation, either version 3 of the License, or
12 (at your option) any later version.
14 simavr is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with simavr. If not, see <http://www.gnu.org/licenses/>.
24 @defgroup avr_bitbang Generic BitBang Module
27 Generic BitBang Module of simavr AVR simulator.
29 @par Features / Implementation Status
30 - easy buffer access with push() / pop() functions
31 - one input and one output pin (can be the same HW pin for I2C)
34 - one input and one output pin (can be the same HW pin for I2C)
35 - one clock pin which can be configured as input or output
36 when the clock is output, the clock signal is generated with a
37 configured frequency (master / slave mode)
38 - 2x 32-bit buffers (input / output) (allows start, stop bits for UART, etc.)
39 - on each read / write a callback is executed to notify the master module
44 #ifndef AVR_BITBANG_H_
45 #define AVR_BITBANG_H_
48 #include "avr_ioport.h"
53 /// SPI Module initialization and state structure
54 typedef struct avr_bitbang_t {
55 avr_t * avr; ///< avr we are attached to
57 uint8_t enabled; ///< bit-bang enabled flag
58 uint8_t clk_generate; ///< generate clock and write to clock pin (if available) -> master / slave mode
59 uint8_t clk_pol; ///< clock polarity, base (inactive) value of clock
60 uint8_t clk_phase; ///< clock phase / data sampling edge
61 /// - 0: data are sampled at first clock edge
62 /// - 1: data are sampled at second clock edge
63 uint32_t clk_cycles; ///< cycles per clock period - must be multiple of 2! (used if clk_generate is enabled)
64 uint8_t data_order; ///< data order / shift
68 uint8_t buffer_size; ///< size of buffer in bits (1...32)
70 void *callback_param; /// anonymous parameter for callback functions
71 void (*callback_bit_read)(uint8_t bit, void *param); ///< callback function to notify about bit read
72 void (*callback_bit_write)(uint8_t bit, void *param); ///< callback function to notify about bit write
73 uint32_t (*callback_transfer_finished)(uint32_t data, void *param); ///< callback function to notify about a complete transfer
74 /// (read received data and write new output data)
76 avr_iopin_t p_clk; ///< clock pin (optional)
77 avr_iopin_t p_in; ///< data in pin
78 avr_iopin_t p_out; ///< data out pin
81 uint32_t data; ///< data buffer
82 /// - latest received bit the is lowest / most right one, bit number: 0
83 /// - next bit to be written is the highest one, bit number: (buffer_size-1)
84 int8_t clk_count; ///< internal clock edge count
88 * reset bitbang sub-module
90 * @param avr avr attached to
91 * @param p bitbang structure
93 void avr_bitbang_reset(avr_t *avr, avr_bitbang_t * p);
96 * start bitbang transfer
98 * buffers should be written / cleared in advanced
99 * timers and interrupts are connected
101 * @param p bitbang structure
103 void avr_bitbang_start(avr_bitbang_t * p);
107 * stop bitbang transfer
109 * timers and interrupts are disabled
111 * @param p bitbang structure
113 void avr_bitbang_stop(avr_bitbang_t * p);
116 #endif /* AVR_BITBANG_H_ */
117 /// @} end of avr_bitbang group