4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
26 * This block respectfully nicked straight out from the Atmel sample
27 * code for AVR315. Typos and all.
28 * There is no copyright notice on the original file.
30 /****************************************************************************
32 ****************************************************************************/
33 // General TWI Master staus codes
34 #define TWI_START 0x08 // START has been transmitted
35 #define TWI_REP_START 0x10 // Repeated START has been transmitted
36 #define TWI_ARB_LOST 0x38 // Arbitration lost
38 // TWI Master Transmitter staus codes
39 #define TWI_MTX_ADR_ACK 0x18 // SLA+W has been tramsmitted and ACK received
40 #define TWI_MTX_ADR_NACK 0x20 // SLA+W has been tramsmitted and NACK received
41 #define TWI_MTX_DATA_ACK 0x28 // Data byte has been tramsmitted and ACK received
42 #define TWI_MTX_DATA_NACK 0x30 // Data byte has been tramsmitted and NACK received
44 // TWI Master Receiver staus codes
45 #define TWI_MRX_ADR_ACK 0x40 // SLA+R has been tramsmitted and ACK received
46 #define TWI_MRX_ADR_NACK 0x48 // SLA+R has been tramsmitted and NACK received
47 #define TWI_MRX_DATA_ACK 0x50 // Data byte has been received and ACK tramsmitted
48 #define TWI_MRX_DATA_NACK 0x58 // Data byte has been received and NACK tramsmitted
50 // TWI Slave Transmitter staus codes
51 #define TWI_STX_ADR_ACK 0xA8 // Own SLA+R has been received; ACK has been returned
52 #define TWI_STX_ADR_ACK_M_ARB_LOST 0xB0 // Arbitration lost in SLA+R/W as Master; own SLA+R has been received; ACK has been returned
53 #define TWI_STX_DATA_ACK 0xB8 // Data byte in TWDR has been transmitted; ACK has been received
54 #define TWI_STX_DATA_NACK 0xC0 // Data byte in TWDR has been transmitted; NOT ACK has been received
55 #define TWI_STX_DATA_ACK_LAST_BYTE 0xC8 // Last data byte in TWDR has been transmitted (TWEA = �0�); ACK has been received
57 // TWI Slave Receiver staus codes
58 #define TWI_SRX_ADR_ACK 0x60 // Own SLA+W has been received ACK has been returned
59 #define TWI_SRX_ADR_ACK_M_ARB_LOST 0x68 // Arbitration lost in SLA+R/W as Master; own SLA+W has been received; ACK has been returned
60 #define TWI_SRX_GEN_ACK 0x70 // General call address has been received; ACK has been returned
61 #define TWI_SRX_GEN_ACK_M_ARB_LOST 0x78 // Arbitration lost in SLA+R/W as Master; General call address has been received; ACK has been returned
62 #define TWI_SRX_ADR_DATA_ACK 0x80 // Previously addressed with own SLA+W; data has been received; ACK has been returned
63 #define TWI_SRX_ADR_DATA_NACK 0x88 // Previously addressed with own SLA+W; data has been received; NOT ACK has been returned
64 #define TWI_SRX_GEN_DATA_ACK 0x90 // Previously addressed with general call; data has been received; ACK has been returned
65 #define TWI_SRX_GEN_DATA_NACK 0x98 // Previously addressed with general call; data has been received; NOT ACK has been returned
66 #define TWI_SRX_STOP_RESTART 0xA0 // A STOP condition or repeated START condition has been received while still addressed as Slave
68 // TWI Miscellaneous status codes
69 #define TWI_NO_STATE 0xF8 // No relevant state information available; TWINT = �0�
70 #define TWI_BUS_ERROR 0x00 // Bus error due to an illegal START or STOP condition
79 avr_regbit_setto_raw(p->io.avr, p->twsr, v);
80 avr_raise_irq(p->io.irq + TWI_IRQ_STATUS, v);
82 avr_raise_interrupt(p->io.avr, &p->twi);
89 return avr_regbit_get_raw(p->io.avr, p->twsr);
92 static avr_cycle_count_t
93 avr_twi_set_state_timer(
95 avr_cycle_count_t when,
98 avr_twi_t * p = (avr_twi_t *)param;
99 _avr_twi_status_set(p, p->next_twstate, 1);
105 _avr_twi_delay_state(
110 p->next_twstate = state;
111 // TODO: calculate clock rate, convert to cycles, and use that
112 avr_cycle_timer_register_usec(
113 p->io.avr, twi_cycles, avr_twi_set_state_timer, p);
123 avr_twi_t * p = (avr_twi_t *)param;
125 uint8_t twen = avr_regbit_get(avr, p->twen);
126 uint8_t twsta = avr_regbit_get(avr, p->twsta);
127 uint8_t twsto = avr_regbit_get(avr, p->twsto);
128 uint8_t twint = avr_regbit_get(avr, p->twi.raised);
130 avr_core_watch_write(avr, addr, v);
132 if (twen != avr_regbit_get(avr, p->twen)) {
134 if (!twen) { // if we were running, now now are not
135 avr_regbit_clear(avr, p->twea);
136 avr_regbit_clear(avr, p->twsta);
137 avr_regbit_clear(avr, p->twsto);
138 avr_clear_interrupt(avr, p->twi.vector);
139 avr_core_watch_write(avr, p->r_twdr, 0xff);
140 _avr_twi_status_set(p, TWI_NO_STATE, 0);
148 int cleared = avr_clear_interupt_if(avr, &p->twi, twint);
150 // clear the interrupt if this bit is now written to 1
152 // interrupt was raised before. The AVR code is acknowledging
153 // something we did, so we go to the next state
155 // interrupt was not raised, were we busy ? we can ignore that
159 if (!twsto && avr_regbit_get(avr, p->twsto)) {
160 // generate a stop condition
162 if (p->state) { // doing stuff
163 if (p->state & TWI_COND_START) {
164 avr_twi_msg_irq_t msg = {
165 .u.twi.msg = TWI_COND_STOP,
166 .u.twi.addr = p->peer_addr,
168 avr_raise_irq(p->io.irq + TWI_IRQ_MOSI, msg.u.v);
173 if (!twsta && avr_regbit_get(avr, p->twsta)) {
174 // generate a start condition
175 if (p->state & TWI_COND_START)
176 _avr_twi_delay_state(p, 3, TWI_REP_START);
178 _avr_twi_delay_state(p, 3, TWI_START);
179 p->state |= TWI_COND_START;
183 !avr_regbit_get(avr, p->twsta) &&
184 !avr_regbit_get(avr, p->twsto)) {
185 // writing or reading a byte
186 if (p->state & TWI_COND_ADDR) {
187 // a normal data byte
188 uint8_t msgv = p->peer_addr & 1 ? TWI_COND_READ : TWI_COND_WRITE;
189 if (avr_regbit_get(avr, p->twea))
190 msgv |= TWI_COND_ACK;
191 avr_twi_msg_irq_t msg = {
193 .u.twi.addr = p->peer_addr,
194 .u.twi.data = avr->data[p->r_twdr],
196 // we send an IRQ and we /expect/ a slave to reply
197 // immediately via an IRQ to set the COND_ACK bit
198 // otherwise it's assumed it's been nacked...
199 avr_raise_irq(p->io.irq + TWI_IRQ_MOSI, msg.u.v);
201 if (p->peer_addr & 1) { // read ?
202 _avr_twi_delay_state(p, 9,
203 p->state & TWI_COND_ACK ?
204 TWI_MTX_DATA_ACK : TWI_MTX_DATA_NACK);
206 _avr_twi_delay_state(p, 9,
207 p->state & TWI_COND_ACK ?
208 TWI_MTX_DATA_ACK : TWI_MTX_DATA_NACK);
213 p->state |= TWI_COND_ADDR;
214 p->peer_addr = avr->data[p->r_twdr];
215 avr_twi_msg_irq_t msg = {
216 .u.twi.msg = TWI_COND_START,
217 .u.twi.addr = p->peer_addr,
219 // we send an IRQ and we /expect/ a slave to reply
220 // immediately via an IRQ tp set the COND_ACK bit
221 // otherwise it's assumed it's been nacked...
222 avr_raise_irq(p->io.irq + TWI_IRQ_MOSI, msg.u.v);
224 if (p->peer_addr & 1) { // read ?
225 _avr_twi_delay_state(p, 9,
226 p->state & TWI_COND_ACK ?
227 TWI_MRX_ADR_ACK : TWI_MRX_ADR_NACK);
229 _avr_twi_delay_state(p, 9,
230 p->state & TWI_COND_ACK ?
231 TWI_MTX_ADR_ACK : TWI_MTX_ADR_NACK);
238 * prevent code from rewriting out status bits, since we actualy use them!
241 avr_twi_write_status(
247 avr_twi_t * p = (avr_twi_t *)param;
248 uint8_t sr = avr_regbit_get(avr, p->twsr);
249 uint8_t c = avr_regbit_get(avr, p->twps);
251 avr_core_watch_write(avr, addr, v);
252 avr_regbit_setto(avr, p->twsr, sr); // force restore
254 if (c != avr_regbit_get(avr, p->twps)) {
255 // prescaler bits changed...
261 struct avr_irq_t * irq,
265 avr_twi_t * p = (avr_twi_t *)param;
266 avr_t * avr = p->io.avr;
268 // check to see if we are enabled
269 if (!avr_regbit_get(avr, p->twen))
279 void avr_twi_reset(struct avr_io_t *io)
281 avr_twi_t * p = (avr_twi_t *)io;
282 avr_irq_register_notify(p->io.irq + TWI_IRQ_MISO, avr_twi_irq_input, p);
285 static avr_io_t _io = {
287 .reset = avr_twi_reset,
290 void avr_twi_init(avr_t * avr, avr_twi_t * p)
293 avr_register_io(avr, &p->io);
294 avr_register_vector(avr, &p->twi);
296 //printf("%s TWI%c init\n", __FUNCTION__, p->name);
298 // allocate this module's IRQ
299 avr_io_setirqs(&p->io, AVR_IOCTL_TWI_GETIRQ(p->name), TWI_IRQ_COUNT, NULL);
301 avr_register_io_write(avr, p->twen.reg, avr_twi_write, p);
302 avr_register_io_write(avr, p->twsr.reg, avr_twi_write_status, p);