5 Right now just handle "write" to the serial port at any speed
6 and printf to the console when '\n' is written.
8 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
10 This file is part of simavr.
12 simavr is free software: you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation, either version 3 of the License, or
15 (at your option) any later version.
17 simavr is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with simavr. If not, see <http://www.gnu.org/licenses/>.
30 #define FONT_GREEN "\e[32m"
31 #define FONT_DEFAULT "\e[0m"
40 DEFINE_FIFO(uint8_t, uart_fifo);
42 static avr_cycle_count_t avr_uart_txc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
44 avr_uart_t * p = (avr_uart_t *)param;
45 if (avr_regbit_get(avr, p->txen)) {
46 // if the interrupts are not used, still raise the UDRE and TXC flag
47 avr_raise_interrupt(avr, &p->udrc);
48 avr_raise_interrupt(avr, &p->txc);
53 static avr_cycle_count_t avr_uart_rxc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
55 avr_uart_t * p = (avr_uart_t *)param;
56 if (avr_regbit_get(avr, p->rxen))
57 avr_raise_interrupt(avr, &p->rxc);
61 static uint8_t avr_uart_rxc_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
63 avr_uart_t * p = (avr_uart_t *)param;
64 uint8_t v = avr_core_watch_read(avr, addr);
66 //static uint8_t old = 0xff; if (v != old) printf("UCSRA read %02x\n", v); old = v;
68 // if RX is enabled, and there is nothing to read, and
69 // the AVR core is reading this register, it's probably
70 // to poll the RXC TXC flag and spinloop
71 // so here we introduce a usleep to make it a bit lighter
72 // on CPU and let data arrive
74 uint8_t ri = !avr_regbit_get(avr, p->rxen) || !avr_regbit_get(avr, p->rxc.raised);
75 uint8_t ti = !avr_regbit_get(avr, p->txen) || !avr_regbit_get(avr, p->txc.raised);
77 if (p->flags & AVR_UART_FLAG_POOL_SLEEP) {
82 // if reception is idle and the fifo is empty, tell whomever there is room
83 if (avr_regbit_get(avr, p->rxen) && uart_fifo_isempty(&p->input)) {
84 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, 0);
85 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XON, 1);
91 static uint8_t avr_uart_read(struct avr_t * avr, avr_io_addr_t addr, void * param)
93 avr_uart_t * p = (avr_uart_t *)param;
95 // clear the rxc bit in case the code is using polling
96 avr_regbit_clear(avr, p->rxc.raised);
98 if (!avr_regbit_get(avr, p->rxen)) {
100 // made to trigger potential watchpoints
101 avr_core_watch_read(avr, addr);
104 uint8_t v = uart_fifo_read(&p->input);
106 //printf("UART read %02x %s\n", v, uart_fifo_isempty(&p->input) ? "EMPTY!" : "");
108 // made to trigger potential watchpoints
109 v = avr_core_watch_read(avr, addr);
111 // trigger timer if more characters are pending
112 if (!uart_fifo_isempty(&p->input))
113 avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p);
118 static void avr_uart_baud_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
120 avr_uart_t * p = (avr_uart_t *)param;
121 avr_core_watch_write(avr, addr, v);
122 uint32_t val = avr->data[p->r_ubrrl] | (avr->data[p->r_ubrrh] << 8);
123 uint32_t baud = avr->frequency / (val+1);
124 if (avr_regbit_get(avr, p->u2x))
129 const int databits[] = { 5,6,7,8, /* 'reserved', assume 8 */8,8,8, 9 };
130 int db = databits[avr_regbit_get(avr, p->ucsz) | (avr_regbit_get(avr, p->ucsz2) << 2)];
131 int sb = 1 + avr_regbit_get(avr, p->usbs);
132 int word_size = 1 /* start */ + db /* data bits */ + 1 /* parity */ + sb /* stops */;
134 printf("UART-%c configured to %04x = %d bps, %d data %d stop\n",
135 p->name, val, baud, db, sb);
136 // TODO: Use the divider value and calculate the straight number of cycles
137 p->usec_per_byte = 1000000 / (baud / word_size);
138 printf("Roughtly %d usec per bytes\n", (int)p->usec_per_byte);
141 static void avr_uart_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
143 avr_uart_t * p = (avr_uart_t *)param;
145 if (addr == p->r_udr) {
146 avr_core_watch_write(avr, addr, v);
149 avr_regbit_clear(avr, p->udrc.raised);
150 avr_cycle_timer_register_usec(avr,
151 p->usec_per_byte, avr_uart_txc_raise, p); // should be uart speed dependent
153 if (p->flags & AVR_UART_FLAG_STDIO) {
154 static char buf[128];
156 buf[l++] = v < ' ' ? '.' : v;
158 if (v == '\n' || l == 127) {
160 printf( FONT_GREEN "%s\n" FONT_DEFAULT, buf);
163 //printf("UDR%c(%02x) = %02x\n", p->name, addr, v);
164 // tell other modules we are "outputing" a byte
165 if (avr_regbit_get(avr, p->txen))
166 avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
168 if (p->udrc.vector && addr == p->udrc.enable.reg) {
170 * If enabling the UDRC interrupt, raise it immediately if FIFO is empty
172 uint8_t udrce = avr_regbit_get(avr, p->udrc.enable);
173 avr_core_watch_write(avr, addr, v);
174 uint8_t nudrce = avr_regbit_get(avr, p->udrc.enable);
175 if (!udrce && nudrce) {
176 // if the FIDO is not empty (clear timer is flying) we don't
177 // need to raise the interrupt, it will happen when the timer
179 if (avr_cycle_timer_status(avr, avr_uart_txc_raise, p) == 0)
180 avr_raise_interrupt(avr, &p->udrc);
183 if (p->udrc.vector && addr == p->udrc.raised.reg) {
184 // get the bits before the write
185 //uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
186 uint8_t txc = avr_regbit_get(avr, p->txc.raised);
188 // no need to write this value in here, only the
189 // interrupt flags need clearing!
190 // avr_core_watch_write(avr, addr, v);
192 //avr_clear_interrupt_if(avr, &p->udrc, udre);
193 avr_clear_interrupt_if(avr, &p->txc, txc);
197 static void avr_uart_irq_input(struct avr_irq_t * irq, uint32_t value, void * param)
199 avr_uart_t * p = (avr_uart_t *)param;
200 avr_t * avr = p->io.avr;
202 // check to see fi receiver is enabled
203 if (!avr_regbit_get(avr, p->rxen))
206 if (uart_fifo_isempty(&p->input))
207 avr_cycle_timer_register_usec(avr, p->usec_per_byte, avr_uart_rxc_raise, p); // should be uart speed dependent
208 uart_fifo_write(&p->input, value); // add to fifo
210 // printf("UART IRQ in %02x (%d/%d) %s\n", value, p->input.read, p->input.write, uart_fifo_isfull(&p->input) ? "FULL!!" : "");
212 if (uart_fifo_isfull(&p->input))
213 avr_raise_irq(p->io.irq + UART_IRQ_OUT_XOFF, 1);
217 void avr_uart_reset(struct avr_io_t *io)
219 avr_uart_t * p = (avr_uart_t *)io;
220 avr_t * avr = p->io.avr;
222 avr_regbit_set(avr, p->udrc.raised);
223 avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
224 avr_cycle_timer_cancel(avr, avr_uart_rxc_raise, p);
225 avr_cycle_timer_cancel(avr, avr_uart_txc_raise, p);
226 uart_fifo_reset(&p->input);
228 // DEBUG allow printf without fidding with enabling the uart
229 avr_regbit_set(avr, p->txen);
230 p->usec_per_byte = 100;
233 static int avr_uart_ioctl(struct avr_io_t * port, uint32_t ctl, void * io_param)
235 avr_uart_t * p = (avr_uart_t *)port;
241 if (ctl == AVR_IOCTL_UART_SET_FLAGS(p->name)) {
242 p->flags = *(uint32_t*)io_param;
245 if (ctl == AVR_IOCTL_UART_GET_FLAGS(p->name)) {
246 *(uint32_t*)io_param = p->flags;
253 static const char * irq_names[UART_IRQ_COUNT] = {
254 [UART_IRQ_INPUT] = "8<in",
255 [UART_IRQ_OUTPUT] = "8>out",
256 [UART_IRQ_OUT_XON] = ">xon",
257 [UART_IRQ_OUT_XOFF] = ">xoff",
260 static avr_io_t _io = {
262 .reset = avr_uart_reset,
263 .ioctl = avr_uart_ioctl,
264 .irq_names = irq_names,
267 void avr_uart_init(avr_t * avr, avr_uart_t * p)
271 // printf("%s UART%c UDR=%02x\n", __FUNCTION__, p->name, p->r_udr);
273 p->flags = AVR_UART_FLAG_POOL_SLEEP|AVR_UART_FLAG_STDIO;
275 avr_register_io(avr, &p->io);
276 avr_register_vector(avr, &p->rxc);
277 avr_register_vector(avr, &p->txc);
278 avr_register_vector(avr, &p->udrc);
280 // allocate this module's IRQ
281 avr_io_setirqs(&p->io, AVR_IOCTL_UART_GETIRQ(p->name), UART_IRQ_COUNT, NULL);
282 // Only call callbacks when the value change...
283 p->io.irq[UART_IRQ_OUT_XOFF].flags |= IRQ_FLAG_FILTERED;
285 avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
286 avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
287 // monitor code that reads the rxc flag, and delay it a bit
288 avr_register_io_read(avr, p->rxc.raised.reg, avr_uart_rxc_read, p);
291 avr_register_io_write(avr, p->udrc.enable.reg, avr_uart_write, p);
293 avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);
295 avr_register_io_write(avr, p->r_ubrrl, avr_uart_baud_write, p);