5 Right now just handle "write" to the serial port at any speed
6 and printf to the console when '\n' is written.
8 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
10 This file is part of simavr.
12 simavr is free software: you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation, either version 3 of the License, or
15 (at your option) any later version.
17 simavr is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with simavr. If not, see <http://www.gnu.org/licenses/>.
29 DEFINE_FIFO(uint8_t, uart_fifo, 128);
31 static void avr_uart_run(avr_io_t * port)
33 avr_uart_t * p = (avr_uart_t *)port;
34 avr_t * avr = p->io.avr;
35 if (p->input_cycle_timer) {
36 p->input_cycle_timer--;
37 if (p->input_cycle_timer == 0) {
38 if (avr_regbit_get(avr, p->rxen))
39 avr_raise_interrupt(avr, &p->rxc);
44 static uint8_t avr_uart_read(struct avr_t * avr, uint8_t addr, void * param)
46 avr_uart_t * p = (avr_uart_t *)param;
48 if (!avr_regbit_get(avr, p->rxen)) {
50 // made to trigger potential watchpoints
51 avr_core_watch_read(avr, addr);
54 uint8_t v = uart_fifo_read(&p->input);
57 // made to trigger potential watchpoints
58 v = avr_core_watch_read(avr, addr);
59 p->input_cycle_timer = uart_fifo_isempty(&p->input) ? 0 : 10;
63 static void avr_uart_write(struct avr_t * avr, uint8_t addr, uint8_t v, void * param)
65 avr_uart_t * p = (avr_uart_t *)param;
67 if (addr == p->r_udr) {
68 // printf("UDR%c(%02x) = %02x\n", p->name, addr, v);
69 avr_core_watch_write(avr, addr, v);
71 // if the interrupts are not used, still raised the UDRE and TXC flaga
72 avr_raise_interrupt(avr, &p->udrc);
73 avr_raise_interrupt(avr, &p->txc);
77 buf[l++] = v < ' ' ? '.' : v;
79 if (v == '\n' || l == 127) {
81 printf("\e[32m%s\e[0m\n", buf);
83 // tell other modules we are "outputing" a byte
84 if (avr_regbit_get(avr, p->txen))
85 avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
87 // get the bits before the write
88 uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
89 uint8_t txc = avr_regbit_get(avr, p->txc.raised);
91 avr_core_watch_write(avr, addr, v);
93 // if writing one to a one, clear bit
94 if (udre && avr_regbit_get(avr, p->udrc.raised))
95 avr_regbit_clear(avr, p->udrc.raised);
96 if (txc && avr_regbit_get(avr, p->txc.raised))
97 avr_regbit_clear(avr, p->txc.raised);
101 static void avr_uart_irq_input(struct avr_irq_t * irq, uint32_t value, void * param)
103 avr_uart_t * p = (avr_uart_t *)param;
104 avr_t * avr = p->io.avr;
106 // check to see fi receiver is enabled
107 if (!avr_regbit_get(avr, p->rxen))
110 uart_fifo_write(&p->input, value); // add to fifo
111 // raise interrupt, if it was not there
112 if (p->input_cycle_timer == 0)
113 p->input_cycle_timer = 10; // random number, should be proportional to speed
117 void avr_uart_reset(struct avr_io_t *io)
119 avr_uart_t * p = (avr_uart_t *)io;
120 avr_t * avr = p->io.avr;
121 avr_regbit_set(avr, p->udrc.raised);
122 avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
123 p->input_cycle_timer = 0;
124 uart_fifo_reset(&p->input);
127 static avr_io_t _io = {
130 .reset = avr_uart_reset,
133 void avr_uart_init(avr_t * avr, avr_uart_t * p)
136 avr_register_io(avr, &p->io);
138 // printf("%s UART%c UDR=%02x\n", __FUNCTION__, p->name, p->r_udr);
140 // allocate this module's IRQ
141 p->io.irq_count = UART_IRQ_COUNT;
142 p->io.irq = avr_alloc_irq(0, p->io.irq_count);
143 p->io.irq_ioctl_get = AVR_IOCTL_UART_GETIRQ(p->name);
145 avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
146 avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
148 avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);