5 Right now just handle "write" to the serial port at any speed
6 and printf to the console when '\n' is written.
8 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
10 This file is part of simavr.
12 simavr is free software: you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation, either version 3 of the License, or
15 (at your option) any later version.
17 simavr is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with simavr. If not, see <http://www.gnu.org/licenses/>.
29 DEFINE_FIFO(uint8_t, uart_fifo, 128);
31 static avr_cycle_count_t avr_uart_rxc_raise(struct avr_t * avr, avr_cycle_count_t when, void * param)
33 avr_uart_t * p = (avr_uart_t *)param;
34 if (avr_regbit_get(avr, p->rxen))
35 avr_raise_interrupt(avr, &p->rxc);
39 static uint8_t avr_uart_read(struct avr_t * avr, uint8_t addr, void * param)
41 avr_uart_t * p = (avr_uart_t *)param;
43 if (!avr_regbit_get(avr, p->rxen)) {
45 // made to trigger potential watchpoints
46 avr_core_watch_read(avr, addr);
49 uint8_t v = uart_fifo_read(&p->input);
52 // made to trigger potential watchpoints
53 v = avr_core_watch_read(avr, addr);
55 if (!uart_fifo_isempty(&p->input))
56 avr_cycle_timer_register_usec(avr, 100, avr_uart_rxc_raise, p); // should be uart speed dependent
61 static void avr_uart_write(struct avr_t * avr, uint8_t addr, uint8_t v, void * param)
63 avr_uart_t * p = (avr_uart_t *)param;
65 if (addr == p->r_udr) {
66 avr_core_watch_write(avr, addr, v);
68 // if the interrupts are not used, still raised the UDRE and TXC flaga
69 avr_raise_interrupt(avr, &p->udrc);
70 avr_raise_interrupt(avr, &p->txc);
74 buf[l++] = v < ' ' ? '.' : v;
76 if (v == '\n' || l == 127) {
78 printf("\e[32m%s\e[0m\n", buf);
80 // printf("UDR%c(%02x) = %02x\n", p->name, addr, v);
81 // tell other modules we are "outputing" a byte
82 if (avr_regbit_get(avr, p->txen))
83 avr_raise_irq(p->io.irq + UART_IRQ_OUTPUT, v);
85 // get the bits before the write
86 uint8_t udre = avr_regbit_get(avr, p->udrc.raised);
87 uint8_t txc = avr_regbit_get(avr, p->txc.raised);
89 avr_core_watch_write(avr, addr, v);
91 // if writing one to a one, clear bit
92 if (udre && avr_regbit_get(avr, p->udrc.raised))
93 avr_regbit_clear(avr, p->udrc.raised);
94 if (txc && avr_regbit_get(avr, p->txc.raised))
95 avr_regbit_clear(avr, p->txc.raised);
99 static void avr_uart_irq_input(struct avr_irq_t * irq, uint32_t value, void * param)
101 avr_uart_t * p = (avr_uart_t *)param;
102 avr_t * avr = p->io.avr;
104 // check to see fi receiver is enabled
105 if (!avr_regbit_get(avr, p->rxen))
108 if (uart_fifo_isempty(&p->input))
109 avr_cycle_timer_register_usec(avr, 100, avr_uart_rxc_raise, p); // should be uart speed dependent
110 uart_fifo_write(&p->input, value); // add to fifo
114 void avr_uart_reset(struct avr_io_t *io)
116 avr_uart_t * p = (avr_uart_t *)io;
117 avr_t * avr = p->io.avr;
118 avr_regbit_set(avr, p->udrc.raised);
119 avr_irq_register_notify(p->io.irq + UART_IRQ_INPUT, avr_uart_irq_input, p);
120 avr_cycle_timer_cancel(avr, avr_uart_rxc_raise, p);
121 uart_fifo_reset(&p->input);
124 static avr_io_t _io = {
126 .reset = avr_uart_reset,
129 void avr_uart_init(avr_t * avr, avr_uart_t * p)
132 avr_register_io(avr, &p->io);
134 // printf("%s UART%c UDR=%02x\n", __FUNCTION__, p->name, p->r_udr);
136 // allocate this module's IRQ
137 p->io.irq_count = UART_IRQ_COUNT;
138 p->io.irq = avr_alloc_irq(0, p->io.irq_count);
139 p->io.irq_ioctl_get = AVR_IOCTL_UART_GETIRQ(p->name);
141 avr_register_io_write(avr, p->r_udr, avr_uart_write, p);
142 avr_register_io_read(avr, p->r_udr, avr_uart_read, p);
144 avr_register_io_write(avr, p->r_ucsra, avr_uart_write, p);