1 /* vim: set sts=4:sw=4:ts=4:noexpandtab
4 Copyright 2012 Torbjorn Tyridal <ttyridal@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
22 /* TODO correct reset values */
23 /* TODO generate sofi every 1ms (when connected) */
24 /* TODO otg support? */
25 /* TODO drop bitfields? */
26 /* TODO thread safe ioctls */
27 /* TODO dual-bank endpoint buffers */
28 /* TODO actually pay attention to endpoint memory allocation ? buggy endpoint configuration doesn't matter in the simulator now. */
146 uint8_t current_bank;
150 struct usb_internal_state {
151 struct _epstate ep_state[5];
152 avr_int_vector_t com_vect;
153 avr_int_vector_t gen_vect;
156 const uint8_t num_endpoints = 5;//sizeof (struct usb_internal_state.ep_state) / sizeof (struct usb_internal_state.ep_state[0]);
162 return p->io.avr->data[p->r_usbcon + uenum];
165 static struct _epstate *
170 assert(ep < num_endpoints);
171 return &p->state->ep_state[ep];
193 struct _epstate * epstate = get_epstate(p, ep);
194 assert(ep < num_endpoints);
195 avr->data[p->r_usbcon + ueint] |= 1 << ep;
202 epstate->ueintx.v |= 1 << irq;
203 if (epstate->ueienx.v & (1 << irq))
204 avr_raise_interrupt(avr, &p->state->com_vect);
207 epstate->ueintx.v |= 1 << irq;
208 if (epstate->ueienx.v & (1 << irq))
209 avr_raise_interrupt(avr, &p->state->com_vect);
212 epstate->uesta0x.overfi = 1;
213 if (epstate->ueienx.flerre)
214 avr_raise_interrupt(avr, &p->state->com_vect);
217 epstate->uesta0x.underfi = 1;
218 if (epstate->ueienx.flerre)
219 avr_raise_interrupt(avr, &p->state->com_vect);
227 suspi = 0, sofi = 2, eorsti = 3, wakeupi = 4, eorsmi = 5, uprsmi = 6
234 uint8_t * Rudien = &p->io.avr->data[p->r_usbcon + udien];
235 uint8_t * Rudint = &p->io.avr->data[p->r_usbcon + udint];
245 if (*Rudien & (1 << irq))
246 avr_raise_interrupt(p->io.avr, &p->state->gen_vect);
259 memset(&p->state->ep_state[1], 0,
260 sizeof p->state->ep_state - sizeof p->state->ep_state[0]);
265 struct _epstate * epstate)
267 return epstate->bank[epstate->current_bank].tail == 0;
272 struct _epstate * epstate)
274 return epstate->bank[epstate->current_bank].tail >=
275 (8 << epstate->uecfg1x.epsize);
280 struct _epstate * epstate)
282 assert(epstate->ueconx.epen);
283 return (8 << epstate->uecfg1x.epsize);
288 struct _epstate * epstate)
290 return epstate->bank[epstate->current_bank].tail;
294 ep_fifo_cpu_readbyte(
295 struct _epstate * epstate)
298 uint8_t v = epstate->bank[epstate->current_bank].bytes[0];
300 if (!epstate->ueconx.epen) {
301 printf("WARNING! Adding bytes to non configured endpoint\n");
305 if (ep_fifo_empty(epstate))
308 for (i = 0, j = ep_fifo_count(epstate) - 1; i < j; i++)
309 epstate->bank[epstate->current_bank].bytes[i] =
310 epstate->bank[epstate->current_bank].bytes[i + 1];
311 epstate->bank[epstate->current_bank].tail--;
316 ep_fifo_cpu_writebyte(
317 struct _epstate * epstate,
320 if (!epstate->ueconx.epen) {
321 printf("WARNING! Adding bytes to non configured endpoint\n");
324 if (ep_fifo_full(epstate))
327 epstate->bank[epstate->current_bank].bytes[epstate->bank[epstate->current_bank].tail++] = v;
333 struct _epstate * epstate,
336 if (!epstate->ueconx.epen) {
337 printf("WARNING! Reading from non configured endpoint\n");
340 if (epstate->ueintx.txini) {
341 return AVR_IOCTL_USB_NAK;
343 if (epstate->ueintx.fifocon && epstate->uecfg0x.eptype != 0) {
344 return AVR_IOCTL_USB_NAK;
347 int ret = epstate->bank[epstate->current_bank].tail;
348 memcpy(buf, epstate->bank[epstate->current_bank].bytes,
349 epstate->bank[epstate->current_bank].tail);
350 epstate->bank[epstate->current_bank].tail = 0;
356 struct _epstate * epstate,
360 if (!epstate->ueconx.epen) {
361 printf("WARNING! Adding bytes to non configured endpoint\n");
365 if (epstate->ueintx.rxouti) {
366 return AVR_IOCTL_USB_NAK;
368 if (epstate->ueintx.fifocon && epstate->uecfg0x.eptype != 0) {
369 return AVR_IOCTL_USB_NAK;
372 if (len > ep_fifo_size(epstate)) {
373 printf("EP OVERFI\n");
374 len = sizeof epstate->bank[epstate->current_bank].bytes;
375 }memcpy(epstate->bank[epstate->current_bank].bytes, buf, len);
376 epstate->bank[epstate->current_bank].tail = len;
382 avr_usb_ep_read_bytecount(
387 avr_usb_t * p = (avr_usb_t *) param;
388 return ep_fifo_count(get_epstate(p, current_ep_to_cpu(p)));
392 avr_usb_udaddr_write(
399 printf("Activate address %d\n", v & 0x7f);
400 avr_core_watch_write(avr, addr, v);
404 avr_usb_udcon_write(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param)
406 avr_usb_t * p = (avr_usb_t *)param;
408 if(avr->data[addr]&1 && !(v&1))
409 avr_raise_irq(p->io.irq + USB_IRQ_ATTACH, !(v&1));
410 avr_core_watch_write(avr, addr, v);
420 assert(v < num_endpoints);
421 avr_core_watch_write(avr, addr, v);
425 avr_usb_ep_read_ueintx(
430 avr_usb_t * p = (avr_usb_t *) param;
431 uint8_t ep = current_ep_to_cpu(p);
433 if (p->state->ep_state[ep].uecfg0x.epdir)
434 p->state->ep_state[ep].ueintx.rwal = !ep_fifo_full(get_epstate(p, ep));
436 p->state->ep_state[ep].ueintx.rwal = !ep_fifo_empty(get_epstate(p, ep));
438 return p->state->ep_state[ep].ueintx.v;
442 avr_usb_ep_write_ueintx(
448 avr_usb_t * p = (avr_usb_t *) param;
449 uint8_t ep = current_ep_to_cpu(p);
451 union _ueintx * newstate = (union _ueintx*) &v;
452 union _ueintx * curstate = &p->state->ep_state[ep].ueintx;
454 if (curstate->rxouti & !newstate->rxouti)
455 curstate->rxouti = 0;
456 if (curstate->txini & !newstate->txini)
458 if (curstate->rxstpi & !newstate->rxstpi) {
460 curstate->rxouti = 0;
461 curstate->rxstpi = 0;
463 if (curstate->fifocon & !newstate->fifocon)
464 curstate->fifocon = 0;
465 if (curstate->nakini & !newstate->nakini)
466 curstate->nakini = 0;
467 if (curstate->nakouti & !newstate->nakouti)
468 curstate->nakouti = 0;
469 if (curstate->stalledi & !newstate->stalledi)
470 curstate->stalledi = 0;
471 if (curstate->rwal & !newstate->rwal)
472 printf("pointless change of ueintx.rwal\n");
474 if ((curstate->v & 0xdf) == 0)
475 avr->data[p->r_usbcon + ueint] &= 0xff ^ (1 << ep); // mark ep0 interrupt
484 avr_usb_t * p = (avr_usb_t *) param;
485 uint8_t laddr = addr - p->r_usbcon;
487 struct _epstate * epstate = get_epstate(p, current_ep_to_cpu(p));
490 case ueconx: v = epstate->ueconx.v; break;
491 case uecfg0x: v = epstate->uecfg0x.v; break;
492 case uecfg1x: v = epstate->uecfg1x.v; break;
493 case uesta0x: v = epstate->uesta0x.v; break;
494 case uesta1x: v = epstate->uesta1x.v; break;
495 case ueienx: v = epstate->ueienx.v; break;
508 avr_usb_t * p = (avr_usb_t *) param;
509 struct _epstate * epstate = get_epstate(p, current_ep_to_cpu(p));
510 uint8_t laddr = addr - p->r_usbcon;
515 epstate->ueconx.stallrq = 0;
517 epstate->ueconx.stallrq = 1;
518 epstate->ueconx.epen = (v & 1) != 0;
521 epstate->uecfg0x.v = v;
522 epstate->uesta0x.cfgok = 0;
525 epstate->uecfg1x.v = v;
526 epstate->uesta0x.cfgok = epstate->uecfg1x.alloc;
527 if (epstate->uecfg0x.eptype == 0)
528 epstate->ueintx.txini = 1;
529 else if (epstate->uecfg0x.epdir) {
530 epstate->ueintx.txini = 1;
531 epstate->ueintx.rwal = 1;
532 epstate->ueintx.fifocon = 1;
534 epstate->ueintx.rxouti = 0;
535 avr_core_watch_write(avr, p->r_usbcon + uesta0x,
539 v = (epstate->uesta0x.v & 0x9f) + (v & (0x60 & epstate->uesta0x.v));
540 epstate->uesta0x.v = v;
543 epstate->ueienx.v = v;
551 avr_usb_ep_read_data(
556 avr_usb_t * p = (avr_usb_t *) param;
557 int ret = ep_fifo_cpu_readbyte(get_epstate(p, current_ep_to_cpu(p)));
561 raise_ep_interrupt(avr, p, current_ep_to_cpu(p), underfi);
564 return (uint8_t) ret;
568 avr_usb_ep_write_data(
574 avr_usb_t * p = (avr_usb_t *) param;
575 int ret = ep_fifo_cpu_writebyte(get_epstate(p, current_ep_to_cpu(p)), v);
580 raise_ep_interrupt(avr, p, current_ep_to_cpu(p), overfi);
591 avr_core_watch_write(avr, addr, v);
598 avr_cycle_count_t when,
601 avr_usb_t * p = (avr_usb_t *) param;
602 //stop sof generation if detached
603 if (avr->data[p->r_usbcon + udcon] & 1)
606 raise_usb_interrupt(p, sofi);
613 struct avr_io_t * io,
617 avr_usb_t * p = (avr_usb_t *) io;
618 struct avr_io_usb * d = (struct avr_io_usb*) io_param;
619 struct _epstate * epstate = 0;
624 case AVR_IOCTL_USB_READ:
626 epstate = get_epstate(p, ep);
628 if (epstate->ueconx.stallrq) {
629 raise_ep_interrupt(io->avr, p, 0, stalledi);
630 return AVR_IOCTL_USB_STALL;
632 if (ep && !epstate->uecfg0x.epdir)
633 printf("Reading from IN endpoint from host??\n");
635 ret = ep_fifo_usb_read(epstate, d->buf);
637 // is this correct? It makes the cdc example work.
638 // Linux stops polling the data ep if we send naks,but
639 // according to usb spec nak'ing should be ok.
640 if (epstate->uecfg0x.eptype == 2) {
648 epstate->ueintx.fifocon = 1;
649 raise_ep_interrupt(io->avr, p, ep, txini);
651 case AVR_IOCTL_USB_WRITE:
653 epstate = get_epstate(p, ep);
655 if (ep && epstate->uecfg0x.epdir)
656 printf("Writing to IN endpoint from host??\n");
658 if (epstate->ueconx.stallrq) {
659 raise_ep_interrupt(io->avr, p, 0, stalledi);
660 return AVR_IOCTL_USB_STALL;
663 ret = ep_fifo_usb_write(epstate, d->buf, d->sz);
667 epstate->ueintx.fifocon = 1;
668 raise_ep_interrupt(io->avr, p, ep, rxouti);
670 case AVR_IOCTL_USB_SETUP:
672 epstate = get_epstate(p, ep);
674 epstate->ueconx.stallrq = 0;
675 // teensy actually depends on this (fails to ack rxouti on usb
676 // control read status stage) even if the datasheet clearly states
677 // that one should do so.
678 epstate->ueintx.rxouti = 0;
680 ret = ep_fifo_usb_write(epstate, d->buf, d->sz);
683 raise_ep_interrupt(io->avr, p, ep, rxstpi);
686 case AVR_IOCTL_USB_RESET:
687 printf("__USB_RESET__\n");
688 reset_endpoints(io->avr, p);
689 raise_usb_interrupt(p, eorsti);
691 avr_cycle_timer_register_usec(io->avr, 1000, sof_generator, p);
702 avr_usb_t * p = (avr_usb_t *) io;
705 memset(p->state->ep_state, 0, sizeof p->state->ep_state);
707 for (i = 0; i < otgtcon; i++)
708 p->io.avr->data[p->r_usbcon + i] = 0;
710 p->io.avr->data[p->r_usbcon] = 0x20;
711 p->io.avr->data[p->r_usbcon + udcon] = 1;
713 printf("%s\n", __FUNCTION__);
716 static const char * irq_names[USB_IRQ_COUNT] = {
717 [USB_IRQ_ATTACH] = ">attach",
722 struct avr_io_t * port)
724 avr_usb_t * p = (avr_usb_t *) port;
728 static avr_io_t _io = {
730 .reset = avr_usb_reset,
731 .irq_names = irq_names,
732 .ioctl = avr_usb_ioctl,
733 .dealloc = avr_usb_dealloc,
737 register_io_ep_readwrite(
742 avr_register_io_write(avr, p->r_usbcon + laddr, avr_usb_ep_write, p);
743 avr_register_io_read(avr, p->r_usbcon + laddr, avr_usb_ep_read, p);
751 // usb interrupts are multiplexed into just two vectors.
752 // we therefore need fake bits for enable & raise
754 // use usbe as fake enable bit
755 p->state->com_vect.enable = (avr_regbit_t)AVR_IO_REGBIT(p->r_usbcon, 7);
756 p->state->gen_vect.enable = (avr_regbit_t)AVR_IO_REGBIT(p->r_usbcon, 7);
758 // // use reserved/unused bits in usbsta as fake raised bits
759 // p->state->com_vect.raised = (avr_regbit_t)AVR_IO_REGBIT(p->r_usbcon+1,7);
760 // p->state->gen_vect.raised = (avr_regbit_t)AVR_IO_REGBIT(p->r_usbcon+1,6);
762 p->state->com_vect.vector = p->usb_com_vect;
763 p->state->gen_vect.vector = p->usb_gen_vect;
765 avr_register_vector(avr, &p->state->com_vect);
766 avr_register_vector(avr, &p->state->gen_vect);
769 void avr_usb_init(avr_t * avr, avr_usb_t * p)
773 p->state = calloc(1, sizeof *p->state);
775 avr_register_io(avr, &p->io);
776 register_vectors(avr, p);
777 // allocate this module's IRQ
778 avr_io_setirqs(&p->io, AVR_IOCTL_USB_GETIRQ(), USB_IRQ_COUNT, NULL);
780 avr_register_io_write(avr, p->r_usbcon + udaddr, avr_usb_udaddr_write, p);
781 avr_register_io_write(avr, p->r_usbcon + udcon, avr_usb_udcon_write, p);
782 avr_register_io_write(avr, p->r_usbcon + uenum, avr_usb_uenum_write, p);
784 avr_register_io_read(avr, p->r_usbcon + uedatx, avr_usb_ep_read_data, p);
785 avr_register_io_write(avr, p->r_usbcon + uedatx, avr_usb_ep_write_data, p);
786 avr_register_io_read(avr, p->r_usbcon + uebclx, avr_usb_ep_read_bytecount, p); //ro
788 avr_register_io_read(avr, p->r_usbcon + ueintx, avr_usb_ep_read_ueintx, p);
789 avr_register_io_write(avr, p->r_usbcon + ueintx, avr_usb_ep_write_ueintx, p);
791 register_io_ep_readwrite(avr, p, ueconx);
792 register_io_ep_readwrite(avr, p, uecfg0x);
793 register_io_ep_readwrite(avr, p, uecfg1x);
794 register_io_ep_readwrite(avr, p, uesta0x);
795 register_io_ep_readwrite(avr, p, uesta1x);
796 register_io_ep_readwrite(avr, p, ueienx);
798 avr_register_io_write(avr, p->r_pllcsr, avr_usb_pll_write, p);