4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
31 typedef uint64_t avr_cycle_count_t;
32 typedef uint16_t avr_io_addr_t;
35 typedef uint8_t (*avr_io_read_t)(struct avr_t * avr, avr_io_addr_t addr, void * param);
36 typedef void (*avr_io_write_t)(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param);
37 typedef avr_cycle_count_t (*avr_cycle_timer_t)(struct avr_t * avr, avr_cycle_count_t when, void * param);
41 S_C = 0,S_Z,S_N,S_V,S_S,S_H,S_T,S_I,
43 // 16 bits register pairs
44 R_XL = 0x1a, R_XH,R_YL,R_YH,R_ZL,R_ZH,
46 R_SPL = 32+0x3d, R_SPH,
50 // maximum number of IO registers, on normal AVRs
51 MAX_IOs = 256 - 32, // minus 32 GP registers
54 #define AVR_DATA_TO_IO(v) ((v) - 32)
55 #define AVR_IO_TO_DATA(v) ((v) + 32)
61 cpu_Limbo = 0, // before initialization is finished
62 cpu_Stopped, // all is stopped, timers included
64 cpu_Running, // we're free running
66 cpu_Sleeping, // we're now sleeping until an interrupt
68 cpu_Step, // run ONE instruction, then...
69 cpu_StepDone, // tell gdb it's all OK, and give it registers
73 * Main AVR instance. Some of these fields are set by the AVR "Core" definition files
74 * the rest is runtime data (as little as possible)
76 typedef struct avr_t {
77 const char * mmcu; // name of the AVR
78 // these are filled by sim_core_declare from constants in /usr/lib/avr/include/avr/io*.h
85 avr_io_addr_t rampz; // optional, only for ELPM/SPM on >64Kb cores
86 avr_io_addr_t eind; // optional, only for EIJMP/EICALL on >64Kb cores
88 // filled by the ELF data, this allow tracking of invalid jumps
91 int state; // stopped, running, sleeping
92 uint32_t frequency; // frequency we are running at
93 // mostly used by the ADC for now
94 uint32_t vcc,avcc,aref; // (optional) voltages in millivolts
96 // cycles gets incremented when sleeping and when running; it corresponds
97 // not only to "cycles that runs" but also "cycles that might have run"
99 avr_cycle_count_t cycle; // current cycle
101 // called at init time
102 void (*init)(struct avr_t * avr);
103 // called at init time (for special purposes like using a memory mapped file as flash see: simduino)
104 void (*special_init)(struct avr_t * avr);
105 // called at termination time ( to clean special initalizations)
106 void (*special_deinit)(struct avr_t * avr);
107 // called at reset time
108 void (*reset)(struct avr_t * avr);
110 // Mirror of the SREG register, to facilitate the access to bits
111 // in the opcode decoder.
112 // This array is re-synthetized back/forth when SREG changes
114 uint8_t i_shadow; // used to detect edges on I flag
118 * Note that the PC is representing /bytes/ while the AVR value is
119 * assumed to be "words". This is in line with what GDB does...
120 * this is why you will see >>1 and <<1 in the decoder to handle jumps.
121 * It CAN be a little confusing, so concentrate, young grasshopper.
126 * callback when specific IO registers are read/written.
127 * There is one drawback here, there is in way of knowing what is the
128 * "beginning of useful sram" on a core, so there is no way to deduce
129 * what is the maximum IO register for a core, and thus, we can't
130 * allocate this table dynamically.
131 * If you wanted to emulate the BIG AVRs, and XMegas, this would need
135 struct avr_irq_t * irq; // optional, used only if asked for with avr_iomem_getirq()
146 // flash memory (initialized to 0xff, and code loaded into it)
148 // this is the general purpose registers, IO registers, and SRAM
151 // queue of io modules
152 struct avr_io_t *io_port;
154 // cycle timers are callbacks that will be called when "when" cycle is reached
155 // the bitmap allows quick knowledge of whether there is anything to call
156 // these timers are one shots, then get cleared if the timer function returns zero,
157 // they get reset if the callback function returns a new cycle number
158 uint32_t cycle_timer_map;
159 avr_cycle_count_t next_cycle_timer;
161 avr_cycle_count_t when;
162 avr_cycle_timer_t timer;
166 // interrupt vectors, and their enable/clear registers
167 struct avr_int_vector_t * vector[64];
168 uint8_t pending_wait; // number of cycles to wait for pending
169 uint32_t pending[2]; // pending interrupts
171 // DEBUG ONLY -- value ignored if CONFIG_SIMAVR_TRACE = 0
174 #if CONFIG_SIMAVR_TRACE
175 struct avr_symbol_t ** codeline;
178 * this keeps track of "jumps" ie, call,jmp,ret,reti and so on
179 * allows dumping of a meaningful data even if the stack is
182 #define OLD_PC_SIZE 32
186 } old[OLD_PC_SIZE]; // catches reset..
190 #define STACK_FRAME_SIZE 32
191 // this records the call/ret pairs, to try to catch
192 // code that munches the stack -under- their own frame
196 } stack_frame[STACK_FRAME_SIZE];
197 int stack_frame_index;
201 // keeps track of which registers gets touched by instructions
202 // reset before each new instructions. Allows meaningful traces
203 uint32_t touched[256 / 32]; // debug
206 // VALUE CHANGE DUMP file (waveforms)
207 // this is the VCD file that gets allocated if the
208 // firmware that is loaded explicitly asks for a trace
209 // to be generated, and allocates it's own symbols
210 // using AVR_MMCU_TAG_VCD_TRACE (see avr_mcu_section.h)
211 struct avr_vcd_t * vcd;
213 // gdb hooking structure. Only present when gdb server is active
214 struct avr_gdb_t * gdb;
216 // if non-zero, the gdb server will be started when the core
217 // crashed even if not activated at startup
218 // if zero, the simulator will just exit() in case of a crash
223 // this is a static constructor for each of the AVR devices
224 typedef struct avr_kind_t {
225 const char * names[4]; // name aliases
229 // a symbol loaded from the .elf file
230 typedef struct avr_symbol_t {
235 // locate the maker for mcu "name" and allocates a new avr instance
236 avr_t * avr_make_mcu_by_name(const char *name);
237 // initializes a new AVR instance. Will call the IO registers init(), and then reset()
238 int avr_init(avr_t * avr);
239 // resets the AVR, and the IO modules
240 void avr_reset(avr_t * avr);
241 // run one cycle of the AVR, sleep if necessary
242 int avr_run(avr_t * avr);
243 // finish any pending operations
244 void avr_terminate(avr_t * avr);
246 // set an IO register to receive commands from the AVR firmware
247 // it's optional, and uses the ELF tags
248 void avr_set_command_register(avr_t * avr, avr_io_addr_t addr);
250 // specify the "console register" -- output sent to this register
251 // is printed on the simulator console, without using a UART
252 void avr_set_console_register(avr_t * avr, avr_io_addr_t addr);
254 // load code in the "flash"
255 void avr_loadcode(avr_t * avr, uint8_t * code, uint32_t size, uint32_t address);
259 * these are accessors for avr->data but allows watchpoints to be set for gdb
260 * IO modules use that to set values to registers, and the AVR core decoder uses
261 * that to register "public" read by instructions.
263 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v);
264 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr);
266 // called when the core has detected a crash somehow.
267 // this might activate gdb server
268 void avr_sadly_crashed(avr_t *avr, uint8_t signal);
275 #include "sim_regbit.h"
276 #include "sim_interrupts.h"
278 #include "sim_cycle_timers.h"
280 #endif /*__SIM_AVR_H__*/