4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
27 typedef uint64_t avr_cycle_count_t;
28 typedef uint16_t avr_io_addr_t;
31 typedef uint8_t (*avr_io_read_t)(struct avr_t * avr, avr_io_addr_t addr, void * param);
32 typedef void (*avr_io_write_t)(struct avr_t * avr, avr_io_addr_t addr, uint8_t v, void * param);
33 typedef avr_cycle_count_t (*avr_cycle_timer_t)(struct avr_t * avr, avr_cycle_count_t when, void * param);
37 S_C = 0,S_Z,S_N,S_V,S_S,S_H,S_T,S_I,
39 // 16 bits register pairs
40 R_XL = 0x1a, R_XH,R_YL,R_YH,R_ZL,R_ZH,
42 R_SPL = 32+0x3d, R_SPH,
46 // maximum number of IO registers, on normal AVRs
47 MAX_IOs = 256 - 32, // minus 32 GP registers
50 #define AVR_DATA_TO_IO(v) ((v) - 32)
51 #define AVR_IO_TO_DATA(v) ((v) + 32)
57 cpu_Limbo = 0, // before initialization is finished
58 cpu_Stopped, // all is stopped, timers included
60 cpu_Running, // we're free running
62 cpu_Sleeping, // we're now sleeping until an interrupt
64 cpu_Step, // run ONE instruction, then...
65 cpu_StepDone, // tell gdb it's all OK, and give it registers
69 * Main AVR instance. Some of these fields are set by the AVR "Core" definition files
70 * the rest is runtime data (as little as possible)
72 typedef struct avr_t {
73 const char * mmcu; // name of the AVR
74 // these are filled by sim_core_declare from constants in /usr/lib/avr/include/avr/io*.h
81 avr_io_addr_t rampz; // optional, only for ELPM/SPM on >64Kb cores
82 avr_io_addr_t eind; // optional, only for EIJMP/EICALL on >64Kb cores
84 // filled by the ELF data, this allow tracking of invalid jumps
87 int state; // stopped, running, sleeping
88 uint32_t frequency; // frequency we are running at
89 // mostly used by the ADC for now
90 uint32_t vcc,avcc,aref; // (optional) voltages
92 // cycles gets incremented when sleeping and when running; it corresponds
93 // not only to "cycles that runs" but also "cycles that might have run"
95 avr_cycle_count_t cycle; // current cycle
97 // called at init time
98 void (*init)(struct avr_t * avr);
99 // called at reset time
100 void (*reset)(struct avr_t * avr);
102 // Mirror of the SREG register, to facilitate the access to bits
103 // in the opcode decoder.
104 // This array is re-synthetized back/forth when SREG changes
106 uint8_t i_shadow; // used to detect edges on I flag
110 * Note that the PC is representing /bytes/ while the AVR value is
111 * assumed to be "words". This is in line with what GDB does...
112 * this is why you will see >>1 and <<1 in the decoder to handle jumps.
113 * It CAN be a little confusing, so concentrate, young grasshopper.
118 * callback when specific IO registers are read/written.
119 * There is one drawback here, there is in way of knowing what is the
120 * "beginning of useful sram" on a core, so there is no way to deduce
121 * what is the maximum IO register for a core, and thus, we can't
122 * allocate this table dynamically.
123 * If you wanted to emulate the BIG AVRs, and XMegas, this would need
127 struct avr_irq_t * irq; // optional, used only if asked for with avr_iomem_getirq()
138 // flash memory (initialized to 0xff, and code loaded into it)
140 // this is the general purpose registers, IO registers, and SRAM
143 // queue of io modules
144 struct avr_io_t *io_port;
146 // cycle timers are callbacks that will be called when "when" cycle is reached
147 // the bitmap allows quick knowledge of whether there is anything to call
148 // these timers are one shots, then get cleared if the timer function returns zero,
149 // they get reset if the callback function returns a new cycle number
150 uint32_t cycle_timer_map;
152 avr_cycle_count_t when;
153 avr_cycle_timer_t timer;
157 // interrupt vectors, and their enable/clear registers
158 struct avr_int_vector_t * vector[64];
159 uint8_t pending_wait; // number of cycles to wait for pending
160 uint32_t pending[2]; // pending interrupts
162 // DEBUG ONLY -- value ignored if CONFIG_SIMAVR_TRACE = 0
165 #if CONFIG_SIMAVR_TRACE
166 struct avr_symbol_t ** codeline;
169 * this keeps track of "jumps" ie, call,jmp,ret,reti and so on
170 * allows dumping of a meaningful data even if the stack is
173 #define OLD_PC_SIZE 32
177 } old[OLD_PC_SIZE]; // catches reset..
181 #define STACK_FRAME_SIZE 32
182 // this records the call/ret pairs, to try to catch
183 // code that munches the stack -under- their own frame
187 } stack_frame[STACK_FRAME_SIZE];
188 int stack_frame_index;
192 // keeps track of which registers gets touched by instructions
193 // reset before each new instructions. Allows meaningful traces
194 uint32_t touched[256 / 32]; // debug
197 // VALUE CHANGE DUMP file (waveforms)
198 // this is the VCD file that gets allocated if the
199 // firmware that is loaded explicitly asks for a trace
200 // to be generated, and allocates it's own symbols
201 // using AVR_MMCU_TAG_VCD_TRACE (see avr_mcu_section.h)
202 struct avr_vcd_t * vcd;
204 // gdb hooking structure. Only present when gdb server is active
205 struct avr_gdb_t * gdb;
207 // if non-zero, the gdb server will be started when the core
208 // crashed even if not activated at startup
209 // if zero, the simulator will just exit() in case of a crash
214 // this is a static constructor for each of the AVR devices
215 typedef struct avr_kind_t {
216 const char * names[4]; // name aliases
220 // a symbol loaded from the .elf file
221 typedef struct avr_symbol_t {
226 // locate the maker for mcu "name" and allocates a new avr instance
227 avr_t * avr_make_mcu_by_name(const char *name);
228 // initializes a new AVR instance. Will call the IO registers init(), and then reset()
229 int avr_init(avr_t * avr);
230 // resets the AVR, and the IO modules
231 void avr_reset(avr_t * avr);
232 // run one cycle of the AVR, sleep if necessary
233 int avr_run(avr_t * avr);
234 // finish any pending operations
235 void avr_terminate(avr_t * avr);
237 // set an IO register to receive commands from the AVR firmware
238 // it's optional, and uses the ELF tags
239 void avr_set_command_register(avr_t * avr, avr_io_addr_t addr);
240 // load code in the "flash"
241 void avr_loadcode(avr_t * avr, uint8_t * code, uint32_t size, uint32_t address);
245 * these are accessors for avr->data but allows watchpoints to be set for gdb
246 * IO modules use that to set values to registers, and the AVR core decoder uses
247 * that to register "public" read by instructions.
249 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v);
250 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr);
252 // called when the core has detected a crash somehow.
253 // this might activate gdb server
254 void avr_sadly_crashed(avr_t *avr, uint8_t signal);
257 #include "sim_regbit.h"
258 #include "sim_interrupts.h"
260 #include "sim_cycle_timers.h"
262 #endif /*__SIM_AVR_H__*/