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   1 /*
   2         sim_core.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25 #include <ctype.h>
  26 #include "sim_avr.h"
  27 #include "sim_core.h"
  28 #include "avr_flash.h"
  29 #include "avr_watchdog.h"
  30
  31 // SREG bit names
  32 const char * _sreg_bit_name = "cznvshti";
  33
  34 /*
  35  * Handle "touching" registers, marking them changed.
  36  * This is used only for debugging purposes to be able to
  37  * print the effects of each instructions on registers
  38  */
  39 #if CONFIG_SIMAVR_TRACE
  40 #define REG_TOUCH(a, r) (a)->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
  41 #define REG_ISTOUCHED(a, r) ((a)->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
  42
  43 /*
  44  * This allows a "special case" to skip indtruction tracing when in these
  45  * symbols. since printf() is useful to have, but generates a lot of cycles
  46  */
  47 int dont_trace(const char * name)
  48 {
  49         return (
  50                 !strcmp(name, "uart_putchar") ||
  51                 !strcmp(name, "fputc") ||
  52                 !strcmp(name, "printf") ||
  53                 !strcmp(name, "vfprintf") ||
  54                 !strcmp(name, "__ultoa_invert") ||
  55                 !strcmp(name, "__prologue_saves__") ||
  56                 !strcmp(name, "__epilogue_restores__"));
  57 }
  58
  59 int donttrace = 0;
  60
  61 #define STATE(_f, args...) { \
  62         if (avr->trace) {\
  63                 if (avr->codeline && avr->codeline[avr->pc>>1]) {\
  64                         const char * symn = avr->codeline[avr->pc>>1]->symbol; \
  65                         int dont = 0 && dont_trace(symn);\
  66                         if (dont!=donttrace) { \
  67                                 donttrace = dont;\
  68                                 DUMP_REG();\
  69                         }\
  70                         if (donttrace==0)\
  71                                 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
  72                 } else \
  73                         printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
  74                 }\
  75         }
  76 #define SREG() if (avr->trace && donttrace == 0) {\
  77         printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
  78         for (int _sbi = 0; _sbi < 8; _sbi++)\
  79                 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
  80         printf("\n");\
  81 }
  82 #else
  83 #define REG_TOUCH(a, r)
  84 #define STATE(_f, args...)
  85 #define SREG()
  86 #endif
  87
  88 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
  89 {
  90         if (addr > avr->ramend) {
  91                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
  92                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  93                 CRASH();
  94         }
  95         if (addr < 32) {
  96                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
  97                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  98                 CRASH();
  99         }
 100 #if AVR_STACK_WATCH
 101         /*
 102          * this checks that the current "function" is not doctoring the stack frame that is located
 103          * higher on the stack than it should be. It's a sign of code that has overrun it's stack
 104          * frame and is munching on it's own return address.
 105          */
 106         if (avr->stack_frame_index > 1 && addr > avr->stack_frame[avr->stack_frame_index-2].sp) {
 107                 printf("\e[31m%04x : munching stack SP %04x, A=%04x <= %02x\e[0m\n", avr->pc, _avr_sp_get(avr), addr, v);
 108         }
 109 #endif
 110         avr->data[addr] = v;
 111 }
 112
 113 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
 114 {
 115         if (addr > avr->ramend) {
 116                 printf("*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n",
 117                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
 118                 CRASH();
 119         }
 120         return avr->data[addr];
 121 }
 122
 123 /*
 124  * Set a register (r < 256)
 125  * if it's an IO regisrer (> 31) also (try to) call any callback that was
 126  * registered to track changes to that register.
 127  */
 128 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
 129 {
 130         REG_TOUCH(avr, r);
 131
 132         if (r == R_SREG) {
 133                 avr->data[r] = v;
 134                 // unsplit the SREG
 135                 for (int i = 0; i < 8; i++)
 136                         avr->sreg[i] = (avr->data[R_SREG] & (1 << i)) != 0;
 137                 SREG();
 138         }
 139         if (r > 31) {
 140                 uint8_t io = AVR_DATA_TO_IO(r);
 141                 if (avr->io[io].w.c)
 142                         avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
 143                 else
 144                         avr->data[r] = v;
 145                 if (avr->io[io].irq) {
 146                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 147                         for (int i = 0; i < 8; i++)
 148                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 149                 }
 150         } else
 151                 avr->data[r] = v;
 152 }
 153
 154 /*
 155  * Stack pointer access
 156  */
 157 inline uint16_t _avr_sp_get(avr_t * avr)
 158 {
 159         return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
 160 }
 161
 162 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
 163 {
 164         _avr_set_r(avr, R_SPL, sp);
 165         _avr_set_r(avr, R_SPH, sp >> 8);
 166 }
 167
 168 /*
 169  * Set any address to a value; split between registers and SRAM
 170  */
 171 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
 172 {
 173         if (addr < 256)
 174                 _avr_set_r(avr, addr, v);
 175         else
 176                 avr_core_watch_write(avr, addr, v);
 177 }
 178
 179 /*
 180  * Get a value from SRAM.
 181  */
 182 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
 183 {
 184         if (addr > 31 && addr < 256) {
 185                 uint8_t io = AVR_DATA_TO_IO(addr);
 186                 if (avr->io[io].r.c)
 187                         avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
 188
 189                 if (avr->io[io].irq) {
 190                         uint8_t v = avr->data[addr];
 191                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 192                         for (int i = 0; i < 8; i++)
 193                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 194                 }
 195         }
 196         return avr_core_watch_read(avr, addr);
 197 }
 198
 199 /*
 200  * Stack push accessors. Push/pop 8 and 16 bits
 201  */
 202 static inline void _avr_push8(avr_t * avr, uint16_t v)
 203 {
 204         uint16_t sp = _avr_sp_get(avr);
 205         _avr_set_ram(avr, sp, v);
 206         _avr_sp_set(avr, sp-1);
 207 }
 208
 209 static inline uint8_t _avr_pop8(avr_t * avr)
 210 {
 211         uint16_t sp = _avr_sp_get(avr) + 1;
 212         uint8_t res = _avr_get_ram(avr, sp);
 213         _avr_sp_set(avr, sp);
 214         return res;
 215 }
 216
 217 inline void _avr_push16(avr_t * avr, uint16_t v)
 218 {
 219         _avr_push8(avr, v >> 8);
 220         _avr_push8(avr, v);
 221 }
 222
 223 static inline uint16_t _avr_pop16(avr_t * avr)
 224 {
 225         uint16_t res = _avr_pop8(avr);
 226         res |= _avr_pop8(avr) << 8;
 227         return res;
 228 }
 229
 230 /*
 231  * "Pretty" register names
 232  */
 233 const char * reg_names[255] = {
 234                 [R_XH] = "XH", [R_XL] = "XL",
 235                 [R_YH] = "YH", [R_YL] = "YL",
 236                 [R_ZH] = "ZH", [R_ZL] = "ZL",
 237                 [R_SPH] = "SPH", [R_SPL] = "SPL",
 238                 [R_SREG] = "SREG",
 239 };
 240
 241
 242 const char * avr_regname(uint8_t reg)
 243 {
 244         if (!reg_names[reg]) {
 245                 char tt[16];
 246                 if (reg < 32)
 247                         sprintf(tt, "r%d", reg);
 248                 else
 249                         sprintf(tt, "io:%02x", reg);
 250                 reg_names[reg] = strdup(tt);
 251         }
 252         return reg_names[reg];
 253 }
 254
 255 /*
 256  * Called when an invalid opcode is decoded
 257  */
 258 static void _avr_invalid_opcode(avr_t * avr)
 259 {
 260 #if CONFIG_SIMAVR_TRACE
 261         printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n",
 262                         avr->pc, avr->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 263 #else
 264         printf("\e[31m*** %04x: Invalid Opcode SP=%04x O=%04x \e[0m\n",
 265                         avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 266 #endif
 267 }
 268
 269 #if CONFIG_SIMAVR_TRACE
 270 /*
 271  * Dump changed registers when tracing
 272  */
 273 void avr_dump_state(avr_t * avr)
 274 {
 275         if (!avr->trace || donttrace)
 276                 return;
 277
 278         int doit = 0;
 279
 280         for (int r = 0; r < 3 && !doit; r++)
 281                 if (avr->touched[r])
 282                         doit = 1;
 283         if (!doit)
 284                 return;
 285         printf("                                       ->> ");
 286         const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
 287         for (int i = 0; i < 4; i++)
 288                 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
 289                         REG_TOUCH(avr, r16[i]);
 290                         REG_TOUCH(avr, r16[i]+1);
 291                 }
 292
 293         for (int i = 0; i < 3*32; i++)
 294                 if (REG_ISTOUCHED(avr, i)) {
 295                         printf("%s=%02x ", avr_regname(i), avr->data[i]);
 296                 }
 297         printf("\n");
 298 }
 299 #endif
 300
 301 #define get_r_d_10(o) \
 302                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 303                 const uint8_t d = (o >> 4) & 0x1f;\
 304                 const uint8_t vd = avr->data[d], vr =avr->data[r];
 305 #define get_k_r16(o) \
 306                 const uint8_t r = 16 + ((o >> 4) & 0xf); \
 307                 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
 308
 309 /*
 310  * Add a "jump" address to the jump trace buffer
 311  */
 312 #if CONFIG_SIMAVR_TRACE
 313 #define TRACE_JUMP()\
 314         avr->old[avr->old_pci].pc = avr->pc;\
 315         avr->old[avr->old_pci].sp = _avr_sp_get(avr);\
 316         avr->old_pci = (avr->old_pci + 1) & (OLD_PC_SIZE-1);\
 317
 318 #if AVR_STACK_WATCH
 319 #define STACK_FRAME_PUSH()\
 320         avr->stack_frame[avr->stack_frame_index].pc = avr->pc;\
 321         avr->stack_frame[avr->stack_frame_index].sp = _avr_sp_get(avr);\
 322         avr->stack_frame_index++;
 323 #define STACK_FRAME_POP()\
 324         if (avr->stack_frame_index > 0) \
 325                 avr->stack_frame_index--;
 326 #else
 327 #define STACK_FRAME_PUSH()
 328 #define STACK_FRAME_POP()
 329 #endif
 330 #else /* CONFIG_SIMAVR_TRACE */
 331
 332 #define TRACE_JUMP()
 333 #define STACK_FRAME_PUSH()
 334 #define STACK_FRAME_POP()
 335
 336 #endif
 337
 338 /****************************************************************************\
 339  *
 340  * Helper functions for calculating the status register bit values.
 341  * See the Atmel data sheet for the instruction set for more info.
 342  *
 343 \****************************************************************************/
 344
 345 static uint8_t
 346 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 347 {
 348     uint8_t resb = res >> b & 0x1;
 349     uint8_t rdb = rd >> b & 0x1;
 350     uint8_t rrb = rr >> b & 0x1;
 351     return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
 352 }
 353
 354 static  uint8_t
 355 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 356 {
 357     uint8_t res7 = res >> 7 & 0x1;
 358     uint8_t rd7 = rd >> 7 & 0x1;
 359     uint8_t rr7 = rr >> 7 & 0x1;
 360     return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
 361 }
 362
 363 static  uint8_t
 364 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 365 {
 366     uint8_t resb = res >> b & 0x1;
 367     uint8_t rdb = rd >> b & 0x1;
 368     uint8_t rrb = rr >> b & 0x1;
 369     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 370 }
 371
 372 static  uint8_t
 373 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 374 {
 375     uint8_t res7 = res >> 7 & 0x1;
 376     uint8_t rd7 = rd >> 7 & 0x1;
 377     uint8_t rr7 = rr >> 7 & 0x1;
 378     return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
 379 }
 380
 381 static  uint8_t
 382 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 383 {
 384     uint8_t resb = (res >> b) & 0x1;
 385     uint8_t rdb = (rd >> b) & 0x1;
 386     uint8_t rrb = (rr >> b) & 0x1;
 387     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 388 }
 389
 390 static  uint8_t
 391 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 392 {
 393     res >>= 7; rd >>= 7; rr >>= 7;
 394     /* The atmel data sheet says the second term is ~rd7 for CP
 395      * but that doesn't make any sense. You be the judge. */
 396     return (rd & ~rr & ~res) | (~rd & rr & res);
 397 }
 398
 399 static inline int _avr_is_instruction_32_bits(avr_t * avr, uint32_t pc)
 400 {
 401         uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
 402         return  o == 0x9200 || // STS ! Store Direct to Data Space
 403                         o == 0x9000 || // LDS Load Direct from Data Space
 404                         o == 0x940c || // JMP Long Jump
 405                         o == 0x940d || // JMP Long Jump
 406                         o == 0x940e ||  // CALL Long Call to sub
 407                         o == 0x940f; // CALL Long Call to sub
 408 }
 409
 410 /*
 411  * Main opcode decoder
 412  *
 413  * The decoder was written by following the datasheet in no particular order.
 414  * As I went along, I noticed "bit patterns" that could be used to factor opcodes
 415  * However, a lot of these only became apparent later on, so SOME instructions
 416  * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
 417  * ones scream to be factored).
 418  * I assume that the decoder could easily be 2/3 of it's current size.
 419  *
 420  * + It lacks the "extended" XMega jumps.
 421  * + It also doesn't check whether the core it's
 422  *   emulating is supposed to have the fancy instructions, like multiply and such.
 423  *
 424  * for now all instructions take "one" cycle, the cycle+=<extra> needs to be added.
 425  */
 426 uint16_t avr_run_one(avr_t * avr)
 427 {
 428 #if CONFIG_SIMAVR_TRACE
 429         /*
 430          * this traces spurious reset or bad jumps
 431          */
 432         if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
 433                 avr->trace = 1;
 434                 STATE("RESET\n");
 435                 CRASH();
 436         }
 437         avr->touched[0] = avr->touched[1] = avr->touched[2] = 0;
 438 #endif
 439
 440         uint32_t        opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
 441         uint32_t        new_pc = avr->pc + 2;   // future "default" pc
 442         int             cycle = 1;
 443
 444         switch (opcode & 0xf000) {
 445                 case 0x0000: {
 446                         switch (opcode) {
 447                                 case 0x0000: {  // NOP
 448                                         STATE("nop\n");
 449                                 }       break;
 450                                 default: {
 451                                         switch (opcode & 0xfc00) {
 452                                                 case 0x0400: {  // CPC compare with carry 0000 01rd dddd rrrr
 453                                                         get_r_d_10(opcode);
 454                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 455                                                         STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 456                                                         if (res)
 457                                                                 avr->sreg[S_Z] = 0;
 458                                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 459                                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 460                                                         avr->sreg[S_N] = (res >> 7) & 1;
 461                                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 462                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 463                                                         SREG();
 464                                                 }       break;
 465                                                 case 0x0c00: {  // ADD without carry 0000 11 rd dddd rrrr
 466                                                         get_r_d_10(opcode);
 467                                                         uint8_t res = vd + vr;
 468                                                         if (r == d) {
 469                                                                 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
 470                                                         } else {
 471                                                                 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 472                                                         }
 473                                                         _avr_set_r(avr, d, res);
 474                                                         avr->sreg[S_Z] = res == 0;
 475                                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 476                                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 477                                                         avr->sreg[S_N] = (res >> 7) & 1;
 478                                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 479                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 480                                                         SREG();
 481                                                 }       break;
 482                                                 case 0x0800: {  // SBC substract with carry 0000 10rd dddd rrrr
 483                                                         get_r_d_10(opcode);
 484                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 485                                                         STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 486                                                         _avr_set_r(avr, d, res);
 487                                                         if (res)
 488                                                                 avr->sreg[S_Z] = 0;
 489                                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 490                                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 491                                                         avr->sreg[S_N] = (res >> 7) & 1;
 492                                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 493                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 494                                                         SREG();
 495                                                 }       break;
 496                                                 default:
 497                                                         switch (opcode & 0xff00) {
 498                                                                 case 0x0100: {  // MOVW – Copy Register Word 0000 0001 dddd rrrr
 499                                                                         uint8_t d = ((opcode >> 4) & 0xf) << 1;
 500                                                                         uint8_t r = ((opcode) & 0xf) << 1;
 501                                                                         STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
 502                                                                         _avr_set_r(avr, d, avr->data[r]);
 503                                                                         _avr_set_r(avr, d+1, avr->data[r+1]);
 504                                                                 }       break;
 505                                                                 case 0x0200: {  // MULS – Multiply Signed 0000 0010 dddd rrrr
 506                                                                         int8_t r = opcode & 0xf;
 507                                                                         int8_t d = (opcode >> 4) & 0xf;
 508                                                                         int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 509                                                                         STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 510                                                                         _avr_set_r(avr, 0, res);
 511                                                                         _avr_set_r(avr, 1, res >> 8);
 512                                                                         avr->sreg[S_C] = (res >> 15) & 1;
 513                                                                         avr->sreg[S_Z] = res == 0;
 514                                                                         SREG();
 515                                                                 }       break;
 516                                                                 case 0x0300: {  // multiplications
 517                                                                         int8_t r = 16 + (opcode & 0x7);
 518                                                                         int8_t d = 16 + ((opcode >> 4) & 0x7);
 519                                                                         int16_t res = 0;
 520                                                                         uint8_t c = 0;
 521                                                                         const char * name = "";
 522                                                                         switch (opcode & 0x88) {
 523                                                                                 case 0x00:      // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
 524                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 525                                                                                         c = (res >> 15) & 1;
 526                                                                                         name = "mulsu";
 527                                                                                         break;
 528                                                                                 case 0x08:      // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
 529                                                                                         res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
 530                                                                                         c = (res >> 15) & 1;
 531                                                                                         res <<= 1;
 532                                                                                         name = "fmul";
 533                                                                                         break;
 534                                                                                 case 0x80:      // FMULS – Multiply Signed  0000 0011 1ddd 0rrr
 535                                                                                         res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 536                                                                                         c = (res >> 15) & 1;
 537                                                                                         res <<= 1;
 538                                                                                         name = "fmuls";
 539                                                                                         break;
 540                                                                                 case 0x88:      // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 0rrr
 541                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 542                                                                                         c = (res >> 15) & 1;
 543                                                                                         res <<= 1;
 544                                                                                         name = "fmulsu";
 545                                                                                         break;
 546                                                                         }
 547                                                                         cycle++;
 548                                                                         STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 549                                                                         _avr_set_r(avr, 0, res);
 550                                                                         _avr_set_r(avr, 1, res >> 8);
 551                                                                         avr->sreg[S_C] = c;
 552                                                                         avr->sreg[S_Z] = res == 0;
 553                                                                         SREG();
 554                                                                 }       break;
 555                                                                 default: _avr_invalid_opcode(avr);
 556                                                         }
 557                                         }
 558                                 }
 559                         }
 560                 }       break;
 561
 562                 case 0x1000: {
 563                         switch (opcode & 0xfc00) {
 564                                 case 0x1800: {  // SUB without carry 0000 10 rd dddd rrrr
 565                                         get_r_d_10(opcode);
 566                                         uint8_t res = vd - vr;
 567                                         STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 568                                         _avr_set_r(avr, d, res);
 569                                         avr->sreg[S_Z] = res == 0;
 570                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 571                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 572                                         avr->sreg[S_N] = (res >> 7) & 1;
 573                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 574                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 575                                         SREG();
 576                                 }       break;
 577                                 case 0x1000: {  // CPSE Compare, skip if equal 0000 10 rd dddd rrrr
 578                                         get_r_d_10(opcode);
 579                                         uint16_t res = vd == vr;
 580                                         STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":"not ");
 581                                         if (res) {
 582                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
 583                                                         new_pc += 4; cycle += 2;
 584                                                 } else {
 585                                                         new_pc += 2; cycle++;
 586                                                 }
 587                                         }
 588                                 }       break;
 589                                 case 0x1400: {  // CP Compare 0000 10 rd dddd rrrr
 590                                         get_r_d_10(opcode);
 591                                         uint8_t res = vd - vr;
 592                                         STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 593                                         avr->sreg[S_Z] = res == 0;
 594                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 595                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 596                                         avr->sreg[S_N] = res >> 7;
 597                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 598                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 599                                         SREG();
 600                                 }       break;
 601                                 case 0x1c00: {  // ADD with carry 0001 11 rd dddd rrrr
 602                                         get_r_d_10(opcode);
 603                                         uint8_t res = vd + vr + avr->sreg[S_C];
 604                                         if (r == d) {
 605                                                 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
 606                                         } else {
 607                                                 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 608                                         }
 609                                         _avr_set_r(avr, d, res);
 610                                         avr->sreg[S_Z] = res == 0;
 611                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 612                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 613                                         avr->sreg[S_N] = (res >> 7) & 1;
 614                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 615                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 616                                         SREG();
 617                                 }       break;
 618                                 default: _avr_invalid_opcode(avr);
 619                         }
 620                 }       break;
 621
 622                 case 0x2000: {
 623                         switch (opcode & 0xfc00) {
 624                                 case 0x2000: {  // AND  0010 00rd dddd rrrr
 625                                         get_r_d_10(opcode);
 626                                         uint8_t res = vd & vr;
 627                                         if (r == d) {
 628                                                 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
 629                                         } else {
 630                                                 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 631                                         }
 632                                         _avr_set_r(avr, d, res);
 633                                         avr->sreg[S_Z] = res == 0;
 634                                         avr->sreg[S_N] = (res >> 7) & 1;
 635                                         avr->sreg[S_V] = 0;
 636                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 637                                         SREG();
 638                                 }       break;
 639                                 case 0x2400: {  // EOR  0010 01rd dddd rrrr
 640                                         get_r_d_10(opcode);
 641                                         uint8_t res = vd ^ vr;
 642                                         if (r==d) {
 643                                                 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
 644                                         } else {
 645                                                 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 646                                         }
 647                                         _avr_set_r(avr, d, res);
 648                                         avr->sreg[S_Z] = res == 0;
 649                                         avr->sreg[S_N] = (res >> 7) & 1;
 650                                         avr->sreg[S_V] = 0;
 651                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 652                                         SREG();
 653                                 }       break;
 654                                 case 0x2800: {  // OR Logical OR        0010 10rd dddd rrrr
 655                                         get_r_d_10(opcode);
 656                                         uint8_t res = vd | vr;
 657                                         STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 658                                         _avr_set_r(avr, d, res);
 659                                         avr->sreg[S_Z] = res == 0;
 660                                         avr->sreg[S_N] = (res >> 7) & 1;
 661                                         avr->sreg[S_V] = 0;
 662                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 663                                         SREG();
 664                                 }       break;
 665                                 case 0x2c00: {  // MOV  0010 11rd dddd rrrr
 666                                         get_r_d_10(opcode);
 667                                         uint8_t res = vr;
 668                                         STATE("mov %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 669                                         _avr_set_r(avr, d, res);
 670                                 }       break;
 671                                 default: _avr_invalid_opcode(avr);
 672                         }
 673                 }       break;
 674
 675                 case 0x3000: {  // CPI 0011 KKKK rrrr KKKK
 676                         get_k_r16(opcode);
 677                         uint8_t vr = avr->data[r];
 678                         uint8_t res = vr - k;
 679                         STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
 680
 681                         avr->sreg[S_Z] = res == 0;
 682                         avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
 683                         avr->sreg[S_V] = get_compare_overflow(res, vr, k);
 684                         avr->sreg[S_N] = (res >> 7) & 1;
 685                         avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
 686                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 687                         SREG();
 688                 }       break;
 689
 690                 case 0x4000: {  // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
 691                         get_k_r16(opcode);
 692                         uint8_t vr = avr->data[r];
 693                         uint8_t res = vr - k - avr->sreg[S_C];
 694                         STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 695                         _avr_set_r(avr, r, res);
 696                         avr->sreg[S_Z] = res  == 0;
 697                         avr->sreg[S_N] = (res >> 7) & 1;
 698                         avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
 699                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 700                         SREG();
 701                 }       break;
 702
 703                 case 0x5000: {  // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
 704                         get_k_r16(opcode);
 705                         uint8_t vr = avr->data[r];
 706                         uint8_t res = vr - k;
 707                         STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 708                         _avr_set_r(avr, r, res);
 709                         avr->sreg[S_Z] = res  == 0;
 710                         avr->sreg[S_N] = (res >> 7) & 1;
 711                         avr->sreg[S_C] = k > vr;
 712                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 713                         SREG();
 714                 }       break;
 715
 716                 case 0x6000: {  // ORI aka SBR  Logical AND with Immediate      0110 kkkk dddd kkkk
 717                         get_k_r16(opcode);
 718                         uint8_t res = avr->data[r] | k;
 719                         STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 720                         _avr_set_r(avr, r, res);
 721                         avr->sreg[S_Z] = res == 0;
 722                         avr->sreg[S_N] = (res >> 7) & 1;
 723                         avr->sreg[S_V] = 0;
 724                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 725                         SREG();
 726                 }       break;
 727
 728                 case 0x7000: {  // ANDI Logical AND with Immediate      0111 kkkk dddd kkkk
 729                         get_k_r16(opcode);
 730                         uint8_t res = avr->data[r] & k;
 731                         STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 732                         _avr_set_r(avr, r, res);
 733                         avr->sreg[S_Z] = res == 0;
 734                         avr->sreg[S_N] = (res >> 7) & 1;
 735                         avr->sreg[S_V] = 0;
 736                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 737                         SREG();
 738                 }       break;
 739
 740                 case 0xa000:
 741                 case 0x8000: {
 742                         switch (opcode & 0xd008) {
 743                                 case 0xa000:
 744                                 case 0x8000: {  // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
 745                                         uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 746                                         uint8_t r = (opcode >> 4) & 0x1f;
 747                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 748
 749                                         if (opcode & 0x0200) {
 750                                                 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 751                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 752                                         } else {
 753                                                 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 754                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 755                                         }
 756                                         cycle += 2;
 757                                 }       break;
 758                                 case 0xa008:
 759                                 case 0x8008: {  // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
 760                                         uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
 761                                         uint8_t r = (opcode >> 4) & 0x1f;
 762                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 763
 764                                         if (opcode & 0x0200) {
 765                                                 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 766                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 767                                         } else {
 768                                                 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 769                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 770                                         }
 771                                         cycle += 2;
 772                                 }       break;
 773                                 default: _avr_invalid_opcode(avr);
 774                         }
 775                 }       break;
 776
 777                 case 0x9000: {
 778                         /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
 779                         if ((opcode & 0xff0f) == 0x9408) {
 780                                 uint8_t b = (opcode >> 4) & 7;
 781                                 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
 782                                 avr->sreg[b] = (opcode & 0x0080) == 0;
 783                                 SREG();
 784                         } else switch (opcode) {
 785                                 case 0x9588: { // SLEEP
 786                                         STATE("sleep\n");
 787                                         avr->state = cpu_Sleeping;
 788                                 }       break;
 789                                 case 0x9598: { // BREAK
 790                                         STATE("break\n");
 791                                         if (avr->gdb) {
 792                                                 // if gdb is on, we break here as in here
 793                                                 // and we do so until gdb restores the instruction
 794                                                 // that was here before
 795                                                 avr->state = cpu_StepDone;
 796                                                 new_pc = avr->pc;
 797                                                 cycle = 0;
 798                                         }
 799                                 }       break;
 800                                 case 0x95a8: { // WDR
 801                                         STATE("wdr\n");
 802                                         avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);
 803                                 }       break;
 804                                 case 0x95e8: { // SPM
 805                                         STATE("spm\n");
 806                                         avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
 807                                 }       break;
 808                                 case 0x9409: { // IJMP Indirect jump
 809                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 810                                         STATE("ijmp Z[%04x]\n", z << 1);
 811                                         new_pc = z << 1;
 812                                         cycle++;
 813                                         TRACE_JUMP();
 814                                 }       break;
 815                                 case 0x9509: { // ICALL Indirect Call to Subroutine
 816                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 817                                         STATE("icall Z[%04x]\n", z << 1);
 818                                         _avr_push16(avr, new_pc >> 1);
 819                                         new_pc = z << 1;
 820                                         cycle += 2;
 821                                         TRACE_JUMP();
 822                                         STACK_FRAME_PUSH();
 823                                 }       break;
 824                                 case 0x9518:    // RETI
 825                                 case 0x9508: {  // RET
 826                                         new_pc = _avr_pop16(avr) << 1;
 827                                         if (opcode & 0x10)      // reti
 828                                                 avr->sreg[S_I] = 1;
 829                                         cycle += 3;
 830                                         STATE("ret%s\n", opcode & 0x10 ? "i" : "");
 831                                         TRACE_JUMP();
 832                                         STACK_FRAME_POP();
 833                                 }       break;
 834                                 case 0x95c8: {  // LPM Load Program Memory R0 <- (Z)
 835                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 836                                         STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
 837                                         _avr_set_r(avr, 0, avr->flash[z]);
 838                                 }       break;
 839                                 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
 840                                 case 0x9478:
 841                                 {       // BSET 1001 0100 0ddd 1000
 842                                         uint8_t b = (opcode >> 4) & 7;
 843                                         avr->sreg[b] = 1;
 844                                         STATE("bset %c\n", _sreg_bit_name[b]);
 845                                         SREG();
 846                                 }       break;
 847                                 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
 848                                 case 0x94f8:
 849                                 {       // BSET 1001 0100 0ddd 1000
 850                                         uint8_t b = (opcode >> 4) & 7;
 851                                         avr->sreg[b] = 0;
 852                                         STATE("bclr %c\n", _sreg_bit_name[b]);
 853                                         SREG();
 854                                 }       break;
 855                                 default:  {
 856                                         switch (opcode & 0xfe0f) {
 857                                                 case 0x9000: {  // LDS Load Direct from Data Space, 32 bits
 858                                                         uint8_t r = (opcode >> 4) & 0x1f;
 859                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 860                                                         new_pc += 2;
 861                                                         STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
 862                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 863                                                         cycle++;
 864                                                 }       break;
 865                                                 case 0x9005:
 866                                                 case 0x9004: {  // LPM Load Program Memory 1001 000d dddd 01oo
 867                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 868                                                         uint8_t r = (opcode >> 4) & 0x1f;
 869                                                         int op = opcode & 3;
 870                                                         STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
 871                                                         _avr_set_r(avr, r, avr->flash[z]);
 872                                                         if (op == 1) {
 873                                                                 z++;
 874                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 875                                                                 _avr_set_r(avr, R_ZL, z);
 876                                                         }
 877                                                         cycle += 2;
 878                                                 }       break;
 879                                                 case 0x900c:
 880                                                 case 0x900d:
 881                                                 case 0x900e: {  // LD Load Indirect from Data using X 1001 000r rrrr 11oo
 882                                                         int op = opcode & 3;
 883                                                         uint8_t r = (opcode >> 4) & 0x1f;
 884                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 885                                                         STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
 886
 887                                                         if (op == 2) x--;
 888                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 889                                                         if (op == 1) x++;
 890                                                         _avr_set_r(avr, R_XH, x >> 8);
 891                                                         _avr_set_r(avr, R_XL, x);
 892                                                 }       break;
 893                                                 case 0x920c:
 894                                                 case 0x920d:
 895                                                 case 0x920e: {  // ST Store Indirect Data Space X 1001 001r rrrr 11oo
 896                                                         int op = opcode & 3;
 897                                                         uint8_t r = (opcode >> 4) & 0x1f;
 898                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 899                                                         STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 900                                                         cycle++;
 901                                                         if (op == 2) x--;
 902                                                         _avr_set_ram(avr, x, avr->data[r]);
 903                                                         if (op == 1) x++;
 904                                                         _avr_set_r(avr, R_XH, x >> 8);
 905                                                         _avr_set_r(avr, R_XL, x);
 906                                                 }       break;
 907                                                 case 0x9009:
 908                                                 case 0x900a: {  // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
 909                                                         int op = opcode & 3;
 910                                                         uint8_t r = (opcode >> 4) & 0x1f;
 911                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 912                                                         STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
 913                                                         cycle++;
 914                                                         if (op == 2) y--;
 915                                                         _avr_set_r(avr, r, _avr_get_ram(avr, y));
 916                                                         if (op == 1) y++;
 917                                                         _avr_set_r(avr, R_YH, y >> 8);
 918                                                         _avr_set_r(avr, R_YL, y);
 919                                                 }       break;
 920                                                 case 0x9209:
 921                                                 case 0x920a: {  // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
 922                                                         int op = opcode & 3;
 923                                                         uint8_t r = (opcode >> 4) & 0x1f;
 924                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 925                                                         STATE("st %sY[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 926                                                         cycle++;
 927                                                         if (op == 2) y--;
 928                                                         _avr_set_ram(avr, y, avr->data[r]);
 929                                                         if (op == 1) y++;
 930                                                         _avr_set_r(avr, R_YH, y >> 8);
 931                                                         _avr_set_r(avr, R_YL, y);
 932                                                 }       break;
 933                                                 case 0x9200: {  // STS ! Store Direct to Data Space, 32 bits
 934                                                         uint8_t r = (opcode >> 4) & 0x1f;
 935                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 936                                                         new_pc += 2;
 937                                                         STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
 938                                                         _avr_set_ram(avr, x, avr->data[r]);
 939                                                 }       break;
 940                                                 case 0x9001:
 941                                                 case 0x9002: {  // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
 942                                                         int op = opcode & 3;
 943                                                         uint8_t r = (opcode >> 4) & 0x1f;
 944                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
 945                                                         STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
 946                                                         if (op == 2) z--;
 947                                                         _avr_set_r(avr, r, _avr_get_ram(avr, z));
 948                                                         if (op == 1) z++;
 949                                                         _avr_set_r(avr, R_ZH, z >> 8);
 950                                                         _avr_set_r(avr, R_ZL, z);
 951                                                 }       break;
 952                                                 case 0x9201:
 953                                                 case 0x9202: {  // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
 954                                                         int op = opcode & 3;
 955                                                         uint8_t r = (opcode >> 4) & 0x1f;
 956                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
 957                                                         STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 958                                                         if (op == 2) z--;
 959                                                         _avr_set_ram(avr, z, avr->data[r]);
 960                                                         if (op == 1) z++;
 961                                                         _avr_set_r(avr, R_ZH, z >> 8);
 962                                                         _avr_set_r(avr, R_ZL, z);
 963                                                 }       break;
 964                                                 case 0x900f: {  // POP 1001 000d dddd 1111
 965                                                         uint8_t r = (opcode >> 4) & 0x1f;
 966                                                         _avr_set_r(avr, r, _avr_pop8(avr));
 967                                                         uint16_t sp = _avr_sp_get(avr);
 968                                                         STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
 969                                                         cycle++;
 970                                                 }       break;
 971                                                 case 0x920f: {  // PUSH 1001 001d dddd 1111
 972                                                         uint8_t r = (opcode >> 4) & 0x1f;
 973                                                         _avr_push8(avr, avr->data[r]);
 974                                                         uint16_t sp = _avr_sp_get(avr);
 975                                                         STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
 976                                                         cycle++;
 977                                                 }       break;
 978                                                 case 0x9400: {  // COM – One’s Complement
 979                                                         uint8_t r = (opcode >> 4) & 0x1f;
 980                                                         uint8_t res = 0xff - avr->data[r];
 981                                                         STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
 982                                                         _avr_set_r(avr, r, res);
 983                                                         avr->sreg[S_Z] = res == 0;
 984                                                         avr->sreg[S_N] = res >> 7;
 985                                                         avr->sreg[S_V] = 0;
 986                                                         avr->sreg[S_C] = 1;
 987                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 988                                                         SREG();
 989                                                 }       break;
 990                                                 case 0x9401: {  // NEG – One’s Complement
 991                                                         uint8_t r = (opcode >> 4) & 0x1f;
 992                                                         uint8_t rd = avr->data[r];
 993                                                         uint8_t res = 0x00 - rd;
 994                                                         STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
 995                                                         _avr_set_r(avr, r, res);
 996                                                         avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
 997                                                         avr->sreg[S_Z] = res == 0;
 998                                                         avr->sreg[S_N] = res >> 7;
 999                                                         avr->sreg[S_V] = res == 0x80;
1000                                                         avr->sreg[S_C] = res != 0;
1001                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1002                                                         SREG();
1003                                                 }       break;
1004                                                 case 0x9402: {  // SWAP – Swap Nibbles
1005                                                         uint8_t r = (opcode >> 4) & 0x1f;
1006                                                         uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1007                                                         STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1008                                                         _avr_set_r(avr, r, res);
1009                                                 }       break;
1010                                                 case 0x9403: {  // INC – Increment
1011                                                         uint8_t r = (opcode >> 4) & 0x1f;
1012                                                         uint8_t res = avr->data[r] + 1;
1013                                                         STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1014                                                         _avr_set_r(avr, r, res);
1015                                                         avr->sreg[S_Z] = res == 0;
1016                                                         avr->sreg[S_N] = res >> 7;
1017                                                         avr->sreg[S_V] = res == 0x7f;
1018                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1019                                                         SREG();
1020                                                 }       break;
1021                                                 case 0x9405: {  // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1022                                                         uint8_t r = (opcode >> 4) & 0x1f;
1023                                                         uint8_t vr = avr->data[r];
1024                                                         uint8_t res = (vr >> 1) | (vr & 0x80);
1025                                                         STATE("asr %s[%02x]\n", avr_regname(r), vr);
1026                                                         _avr_set_r(avr, r, res);
1027                                                         avr->sreg[S_Z] = res == 0;
1028                                                         avr->sreg[S_C] = vr & 1;
1029                                                         avr->sreg[S_N] = res >> 7;
1030                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1031                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1032                                                         SREG();
1033                                                 }       break;
1034                                                 case 0x9406: {  // LSR 1001 010d dddd 0110
1035                                                         uint8_t r = (opcode >> 4) & 0x1f;
1036                                                         uint8_t vr = avr->data[r];
1037                                                         uint8_t res = vr >> 1;
1038                                                         STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1039                                                         _avr_set_r(avr, r, res);
1040                                                         avr->sreg[S_Z] = res == 0;
1041                                                         avr->sreg[S_C] = vr & 1;
1042                                                         avr->sreg[S_N] = 0;
1043                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1044                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1045                                                         SREG();
1046                                                 }       break;
1047                                                 case 0x9407: {  // ROR 1001 010d dddd 0111
1048                                                         uint8_t r = (opcode >> 4) & 0x1f;
1049                                                         uint8_t vr = avr->data[r];
1050                                                         uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1051                                                         STATE("ror %s[%02x]\n", avr_regname(r), vr);
1052                                                         _avr_set_r(avr, r, res);
1053                                                         avr->sreg[S_Z] = res == 0;
1054                                                         avr->sreg[S_C] = vr & 1;
1055                                                         avr->sreg[S_N] = 0;
1056                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1057                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1058                                                         SREG();
1059                                                 }       break;
1060                                                 case 0x940a: {  // DEC – Decrement
1061                                                         uint8_t r = (opcode >> 4) & 0x1f;
1062                                                         uint8_t res = avr->data[r] - 1;
1063                                                         STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1064                                                         _avr_set_r(avr, r, res);
1065                                                         avr->sreg[S_Z] = res == 0;
1066                                                         avr->sreg[S_N] = res >> 7;
1067                                                         avr->sreg[S_V] = res == 0x80;
1068                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1069                                                         SREG();
1070                                                 }       break;
1071                                                 case 0x940c:
1072                                                 case 0x940d: {  // JMP Long Call to sub, 32 bits
1073                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1074                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1075                                                         a = (a << 16) | x;
1076                                                         STATE("jmp 0x%06x\n", a);
1077                                                         new_pc = a << 1;
1078                                                         cycle += 2;
1079                                                         TRACE_JUMP();
1080                                                 }       break;
1081                                                 case 0x940e:
1082                                                 case 0x940f: {  // CALL Long Call to sub, 32 bits
1083                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1084                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1085                                                         a = (a << 16) | x;
1086                                                         STATE("call 0x%06x\n", a);
1087                                                         new_pc += 2;
1088                                                         _avr_push16(avr, new_pc >> 1);
1089                                                         new_pc = a << 1;
1090                                                         cycle += 3;     // 4 cycles
1091                                                         TRACE_JUMP();
1092                                                         STACK_FRAME_PUSH();
1093                                                 }       break;
1094
1095                                                 default: {
1096                                                         switch (opcode & 0xff00) {
1097                                                                 case 0x9600: {  // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1098                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1099                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1100                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1101                                                                         uint32_t res = rdl | (rdh << 8);
1102                                                                         STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1103                                                                         res += k;
1104                                                                         _avr_set_r(avr, r + 1, res >> 8);
1105                                                                         _avr_set_r(avr, r, res);
1106                                                                         avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1107                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1108                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1109                                                                         avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1110                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1111                                                                         SREG();
1112                                                                         cycle++;
1113                                                                 }       break;
1114                                                                 case 0x9700: {  // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1115                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1116                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1117                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1118                                                                         uint32_t res = rdl | (rdh << 8);
1119                                                                         STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1120                                                                         res -= k;
1121                                                                         _avr_set_r(avr, r + 1, res >> 8);
1122                                                                         _avr_set_r(avr, r, res);
1123                                                                         avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1124                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1125                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1126                                                                         avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1127                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1128                                                                         SREG();
1129                                                                         cycle++;
1130                                                                 }       break;
1131                                                                 case 0x9800: {  // CBI - Clear Bit in I/O Registe 1001 1000 AAAA Abbb
1132                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1133                                                                         uint8_t b = opcode & 0x7;
1134                                                                         uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1135                                                                         STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1136                                                                         _avr_set_ram(avr, io, res);
1137                                                                         cycle++;
1138                                                                 }       break;
1139                                                                 case 0x9900: {  // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1140                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1141                                                                         uint8_t b = opcode & 0x7;
1142                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1143                                                                         STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":"not ");
1144                                                                         if (!res) {
1145                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1146                                                                                         new_pc += 4; cycle += 2;
1147                                                                                 } else {
1148                                                                                         new_pc += 2; cycle++;
1149                                                                                 }
1150                                                                         }
1151                                                                 }       break;
1152                                                                 case 0x9a00: {  // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1153                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1154                                                                         uint8_t b = opcode & 0x7;
1155                                                                         uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1156                                                                         STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1157                                                                         _avr_set_ram(avr, io, res);
1158                                                                         cycle++;
1159                                                                 }       break;
1160                                                                 case 0x9b00: {  // SBIS - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1161                                                                         uint8_t io = (opcode >> 3) & 0x1f;
1162                                                                         uint8_t b = opcode & 0x7;
1163                                                                         uint8_t res = _avr_get_ram(avr, io + 32) & (1 << b);
1164                                                                         STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":"not ");
1165                                                                         if (res) {
1166                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1167                                                                                         new_pc += 4; cycle += 2;
1168                                                                                 } else {
1169                                                                                         new_pc += 2; cycle++;
1170                                                                                 }
1171                                                                         }
1172                                                                 }       break;
1173                                                                 default:
1174                                                                         switch (opcode & 0xfc00) {
1175                                                                                 case 0x9c00: {  // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1176                                                                                         get_r_d_10(opcode);
1177                                                                                         uint16_t res = vd * vr;
1178                                                                                         STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1179                                                                                         _avr_set_r(avr, 0, res);
1180                                                                                         _avr_set_r(avr, 1, res >> 8);
1181                                                                                         avr->sreg[S_Z] = res == 0;
1182                                                                                         avr->sreg[S_C] = (res >> 15) & 1;
1183                                                                                         SREG();
1184                                                                                 }       break;
1185                                                                                 default: _avr_invalid_opcode(avr);
1186                                                                         }
1187                                                         }
1188                                                 }       break;
1189                                         }
1190                                 }       break;
1191                         }
1192                 }       break;
1193
1194                 case 0xb000: {
1195                         switch (opcode & 0xf800) {
1196                                 case 0xb800: {  // OUT A,Rr 1011 1AAr rrrr AAAA
1197                                         uint8_t r = (opcode >> 4) & 0x1f;
1198                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1199                                         STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1200                                         // todo: store to IO register
1201                                         _avr_set_ram(avr, A, avr->data[r]);
1202                                 //      avr->data[A] = ;
1203                                 }       break;
1204                                 case 0xb000: {  // IN Rd,A 1011 0AAr rrrr AAAA
1205                                         uint8_t r = (opcode >> 4) & 0x1f;
1206                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1207                                         STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1208                                         // todo: get the IO register
1209                                         _avr_set_r(avr, r, _avr_get_ram(avr, A));
1210                                 }       break;
1211                                 default: _avr_invalid_opcode(avr);
1212                         }
1213                 }       break;
1214
1215                 case 0xc000: {
1216                         // RJMP 1100 kkkk kkkk kkkk
1217                         short o = ((short)(opcode << 4)) >> 4;
1218                         STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1219                         new_pc = new_pc + (o << 1);
1220                         cycle++;
1221                         TRACE_JUMP();
1222                 }       break;
1223
1224                 case 0xd000: {
1225                         // RCALL 1100 kkkk kkkk kkkk
1226                         short o = ((short)(opcode << 4)) >> 4;
1227                         STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1228                         _avr_push16(avr, new_pc >> 1);
1229                         new_pc = new_pc + (o << 1);
1230                         cycle += 2;
1231                         // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1232                         if (o != 0) {
1233                                 TRACE_JUMP();
1234                                 STACK_FRAME_PUSH();
1235                         }
1236                 }       break;
1237
1238                 case 0xe000: {  // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1239                         uint8_t d = 16 + ((opcode >> 4) & 0xf);
1240                         uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1241                         STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1242                         _avr_set_r(avr, d, k);
1243                 }       break;
1244
1245                 case 0xf000: {
1246                         switch (opcode & 0xfe00) {
1247                                 case 0xf000:
1248                                 case 0xf200:
1249                                 case 0xf400:
1250                                 case 0xf600: {  // All the SREG branches
1251                                         short o = ((short)(opcode << 6)) >> 9; // offset
1252                                         uint8_t s = opcode & 7;
1253                                         int set = (opcode & 0x0400) == 0;               // this bit means BRXC otherwise BRXS
1254                                         int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1255                                         const char *names[2][8] = {
1256                                                         { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1257                                                         { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1258                                         };
1259                                         if (names[set][s]) {
1260                                                 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1261                                         } else {
1262                                                 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1263                                         }
1264                                         if (branch) {
1265                                                 cycle++;
1266                                                 new_pc = new_pc + (o << 1);
1267                                         }
1268                                 }       break;
1269                                 case 0xf800:
1270                                 case 0xf900: {  // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1271                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1272                                         uint8_t s = opcode & 7;
1273                                         uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1274                                         STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1275                                         _avr_set_r(avr, r, v);
1276                                 }       break;
1277                                 case 0xfa00:
1278                                 case 0xfb00:{   // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1279                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1280                                         uint8_t s = opcode & 7;
1281                                         STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1282                                         avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1283                                         SREG();
1284                                 }       break;
1285                                 case 0xfc00:
1286                                 case 0xfe00: {  // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1287                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1288                                         uint8_t s = opcode & 7;
1289                                         int set = (opcode & 0x0200) != 0;
1290                                         int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1291                                         STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1292                                         if (branch)
1293                                                 new_pc = new_pc + 2;
1294                                 }       break;
1295                                 default: _avr_invalid_opcode(avr);
1296                         }
1297                 }       break;
1298
1299                 default: _avr_invalid_opcode(avr);
1300
1301         }
1302         avr->cycle += cycle;
1303         return new_pc;
1304 }
1305
1306