git.rot13.org Git - simavr/blob - simavr/sim/sim_core.c

   1 /*
   2         sim_core.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25 #include <ctype.h>
  26 #include "sim_avr.h"
  27 #include "sim_core.h"
  28 #include "avr_flash.h"
  29
  30 // SREG bit names
  31 const char * _sreg_bit_name = "cznvshti";
  32
  33 /*
  34  * Handle "touching" registers, marking them changed.
  35  * This is used only for debugging purposes to be able to
  36  * print the effects of each instructions on registers
  37  */
  38 #if CONFIG_SIMAVR_TRACE
  39 #define REG_TOUCH(a, r) (a)->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
  40 #define REG_ISTOUCHED(a, r) ((a)->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
  41
  42 /*
  43  * This allows a "special case" to skip indtruction tracing when in these
  44  * symbols. since printf() is useful to have, but generates a lot of cycles
  45  */
  46 int dont_trace(const char * name)
  47 {
  48         return (
  49                 !strcmp(name, "uart_putchar") ||
  50                 !strcmp(name, "fputc") ||
  51                 !strcmp(name, "printf") ||
  52                 !strcmp(name, "vfprintf") ||
  53                 !strcmp(name, "__ultoa_invert") ||
  54                 !strcmp(name, "__prologue_saves__") ||
  55                 !strcmp(name, "__epilogue_restores__"));
  56 }
  57
  58 int donttrace = 0;
  59
  60 #define STATE(_f, args...) { \
  61         if (avr->trace) {\
  62                 if (avr->codeline && avr->codeline[avr->pc>>1]) {\
  63                         const char * symn = avr->codeline[avr->pc>>1]->symbol; \
  64                         int dont = 0 && dont_trace(symn);\
  65                         if (dont!=donttrace) { \
  66                                 donttrace = dont;\
  67                                 DUMP_REG();\
  68                         }\
  69                         if (donttrace==0)\
  70                                 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
  71                 } else \
  72                         printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
  73                 }\
  74         }
  75 #define SREG() if (avr->trace && donttrace == 0) {\
  76         printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
  77         for (int _sbi = 0; _sbi < 8; _sbi++)\
  78                 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
  79         printf("\n");\
  80 }
  81 #else
  82 #define REG_TOUCH(a, r)
  83 #define STATE(_f, args...)
  84 #define SREG()
  85 #endif
  86
  87 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
  88 {
  89         if (addr > avr->ramend) {
  90                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
  91                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  92                 CRASH();
  93         }
  94         if (addr < 32) {
  95                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
  96                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  97                 CRASH();
  98         }
  99 #if AVR_STACK_WATCH
 100         /*
 101          * this checks that the current "function" is not doctoring the stack frame that is located
 102          * higher on the stack than it should be. It's a sign of code that has overrun it's stack
 103          * frame and is munching on it's own return address.
 104          */
 105         if (avr->stack_frame_index > 1 && addr > avr->stack_frame[avr->stack_frame_index-2].sp) {
 106                 printf("\e[31m%04x : munching stack SP %04x, A=%04x <= %02x\e[0m\n", avr->pc, _avr_sp_get(avr), addr, v);
 107         }
 108 #endif
 109         avr->data[addr] = v;
 110 }
 111
 112 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
 113 {
 114         if (addr > avr->ramend) {
 115                 printf("*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n",
 116                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
 117                 CRASH();
 118         }
 119         return avr->data[addr];
 120 }
 121
 122 /*
 123  * Set a register (r < 256)
 124  * if it's an IO regisrer (> 31) also (try to) call any callback that was
 125  * registered to track changes to that register.
 126  */
 127 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
 128 {
 129         REG_TOUCH(avr, r);
 130
 131         if (r == R_SREG) {
 132                 avr->data[r] = v;
 133                 // unsplit the SREG
 134                 for (int i = 0; i < 8; i++)
 135                         avr->sreg[i] = (avr->data[R_SREG] & (1 << i)) != 0;
 136                 SREG();
 137         }
 138         if (r > 31) {
 139                 uint8_t io = AVR_DATA_TO_IO(r);
 140                 if (avr->io[io].w.c)
 141                         avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
 142                 else
 143                         avr->data[r] = v;
 144                 if (avr->io[io].irq) {
 145                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 146                         for (int i = 0; i < 8; i++)
 147                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 148                 }
 149         } else
 150                 avr->data[r] = v;
 151 }
 152
 153 /*
 154  * Stack pointer access
 155  */
 156 inline uint16_t _avr_sp_get(avr_t * avr)
 157 {
 158         return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
 159 }
 160
 161 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
 162 {
 163         _avr_set_r(avr, R_SPL, sp);
 164         _avr_set_r(avr, R_SPH, sp >> 8);
 165 }
 166
 167 /*
 168  * Set any address to a value; split between registers and SRAM
 169  */
 170 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
 171 {
 172         if (addr < 256)
 173                 _avr_set_r(avr, addr, v);
 174         else
 175                 avr_core_watch_write(avr, addr, v);
 176 }
 177
 178 /*
 179  * Get a value from SRAM.
 180  */
 181 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
 182 {
 183         if (addr > 31 && addr < 256) {
 184                 uint8_t io = AVR_DATA_TO_IO(addr);
 185                 if (avr->io[io].r.c)
 186                         avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
 187
 188                 if (avr->io[io].irq) {
 189                         uint8_t v = avr->data[addr];
 190                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 191                         for (int i = 0; i < 8; i++)
 192                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 193                 }
 194         }
 195         return avr_core_watch_read(avr, addr);
 196 }
 197
 198 /*
 199  * Stack push accessors. Push/pop 8 and 16 bits
 200  */
 201 static inline void _avr_push8(avr_t * avr, uint16_t v)
 202 {
 203         uint16_t sp = _avr_sp_get(avr);
 204         _avr_set_ram(avr, sp, v);
 205         _avr_sp_set(avr, sp-1);
 206 }
 207
 208 static inline uint8_t _avr_pop8(avr_t * avr)
 209 {
 210         uint16_t sp = _avr_sp_get(avr) + 1;
 211         uint8_t res = _avr_get_ram(avr, sp);
 212         _avr_sp_set(avr, sp);
 213         return res;
 214 }
 215
 216 inline void _avr_push16(avr_t * avr, uint16_t v)
 217 {
 218         _avr_push8(avr, v >> 8);
 219         _avr_push8(avr, v);
 220 }
 221
 222 static inline uint16_t _avr_pop16(avr_t * avr)
 223 {
 224         uint16_t res = _avr_pop8(avr);
 225         res |= _avr_pop8(avr) << 8;
 226         return res;
 227 }
 228
 229 /*
 230  * "Pretty" register names
 231  */
 232 const char * reg_names[255] = {
 233                 [R_XH] = "XH", [R_XL] = "XL",
 234                 [R_YH] = "YH", [R_YL] = "YL",
 235                 [R_ZH] = "ZH", [R_ZL] = "ZL",
 236                 [R_SPH] = "SPH", [R_SPL] = "SPL",
 237                 [R_SREG] = "SREG",
 238 };
 239
 240
 241 const char * avr_regname(uint8_t reg)
 242 {
 243         if (!reg_names[reg]) {
 244                 char tt[16];
 245                 if (reg < 32)
 246                         sprintf(tt, "r%d", reg);
 247                 else
 248                         sprintf(tt, "io:%02x", reg);
 249                 reg_names[reg] = strdup(tt);
 250         }
 251         return reg_names[reg];
 252 }
 253
 254 /*
 255  * Called when an invalid opcode is decoded
 256  */
 257 static void _avr_invalid_opcode(avr_t * avr)
 258 {
 259 #if CONFIG_SIMAVR_TRACE
 260         printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n",
 261                         avr->pc, avr->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 262 #else
 263         printf("\e[31m*** %04x: Invalid Opcode SP=%04x O=%04x \e[0m\n",
 264                         avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 265 #endif
 266 }
 267
 268 #if CONFIG_SIMAVR_TRACE
 269 /*
 270  * Dump changed registers when tracing
 271  */
 272 void avr_dump_state(avr_t * avr)
 273 {
 274         if (!avr->trace || donttrace)
 275                 return;
 276
 277         int doit = 0;
 278
 279         for (int r = 0; r < 3 && !doit; r++)
 280                 if (avr->touched[r])
 281                         doit = 1;
 282         if (!doit)
 283                 return;
 284         printf("                                       ->> ");
 285         const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
 286         for (int i = 0; i < 4; i++)
 287                 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
 288                         REG_TOUCH(avr, r16[i]);
 289                         REG_TOUCH(avr, r16[i]+1);
 290                 }
 291
 292         for (int i = 0; i < 3*32; i++)
 293                 if (REG_ISTOUCHED(avr, i)) {
 294                         printf("%s=%02x ", avr_regname(i), avr->data[i]);
 295                 }
 296         printf("\n");
 297 }
 298 #endif
 299
 300 #define get_r_d_10(o) \
 301                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 302                 const uint8_t d = (o >> 4) & 0x1f;\
 303                 const uint8_t vd = avr->data[d], vr =avr->data[r];
 304 #define get_k_r16(o) \
 305                 const uint8_t r = 16 + ((o >> 4) & 0xf); \
 306                 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
 307
 308 /*
 309  * Add a "jump" address to the jump trace buffer
 310  */
 311 #if CONFIG_SIMAVR_TRACE
 312 #define TRACE_JUMP()\
 313         avr->old[avr->old_pci].pc = avr->pc;\
 314         avr->old[avr->old_pci].sp = _avr_sp_get(avr);\
 315         avr->old_pci = (avr->old_pci + 1) & (OLD_PC_SIZE-1);\
 316
 317 #if AVR_STACK_WATCH
 318 #define STACK_FRAME_PUSH()\
 319         avr->stack_frame[avr->stack_frame_index].pc = avr->pc;\
 320         avr->stack_frame[avr->stack_frame_index].sp = _avr_sp_get(avr);\
 321         avr->stack_frame_index++;
 322 #define STACK_FRAME_POP()\
 323         if (avr->stack_frame_index > 0) \
 324                 avr->stack_frame_index--;
 325 #else
 326 #define STACK_FRAME_PUSH()
 327 #define STACK_FRAME_POP()
 328 #endif
 329 #else /* CONFIG_SIMAVR_TRACE */
 330
 331 #define TRACE_JUMP()
 332 #define STACK_FRAME_PUSH()
 333 #define STACK_FRAME_POP()
 334
 335 #endif
 336
 337 /****************************************************************************\
 338  *
 339  * Helper functions for calculating the status register bit values.
 340  * See the Atmel data sheet for the instruction set for more info.
 341  *
 342 \****************************************************************************/
 343
 344 static uint8_t
 345 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 346 {
 347     uint8_t resb = res >> b & 0x1;
 348     uint8_t rdb = rd >> b & 0x1;
 349     uint8_t rrb = rr >> b & 0x1;
 350     return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
 351 }
 352
 353 static  uint8_t
 354 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 355 {
 356     uint8_t res7 = res >> 7 & 0x1;
 357     uint8_t rd7 = rd >> 7 & 0x1;
 358     uint8_t rr7 = rr >> 7 & 0x1;
 359     return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
 360 }
 361
 362 static  uint8_t
 363 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 364 {
 365     uint8_t resb = res >> b & 0x1;
 366     uint8_t rdb = rd >> b & 0x1;
 367     uint8_t rrb = rr >> b & 0x1;
 368     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 369 }
 370
 371 static  uint8_t
 372 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 373 {
 374     uint8_t res7 = res >> 7 & 0x1;
 375     uint8_t rd7 = rd >> 7 & 0x1;
 376     uint8_t rr7 = rr >> 7 & 0x1;
 377     return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
 378 }
 379
 380 static  uint8_t
 381 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 382 {
 383     uint8_t resb = (res >> b) & 0x1;
 384     uint8_t rdb = (rd >> b) & 0x1;
 385     uint8_t rrb = (rr >> b) & 0x1;
 386     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 387 }
 388
 389 static  uint8_t
 390 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 391 {
 392     res >>= 7; rd >>= 7; rr >>= 7;
 393     /* The atmel data sheet says the second term is ~rd7 for CP
 394      * but that doesn't make any sense. You be the judge. */
 395     return (rd & ~rr & ~res) | (~rd & rr & res);
 396 }
 397
 398 static inline int _avr_is_instruction_32_bits(avr_t * avr, uint32_t pc)
 399 {
 400         uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
 401         return  o == 0x9200 || // STS ! Store Direct to Data Space
 402                         o == 0x9000 || // LDS Load Direct from Data Space
 403                         o == 0x940c || // JMP Long Jump
 404                         o == 0x940d || // JMP Long Jump
 405                         o == 0x940e ||  // CALL Long Call to sub
 406                         o == 0x940f; // CALL Long Call to sub
 407 }
 408
 409 /*
 410  * Main opcode decoder
 411  *
 412  * The decoder was written by following the datasheet in no particular order.
 413  * As I went along, I noticed "bit patterns" that could be used to factor opcodes
 414  * However, a lot of these only became apparent later on, so SOME instructions
 415  * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
 416  * ones scream to be factored).
 417  * I assume that the decoder could easily be 2/3 of it's current size.
 418  *
 419  * + It lacks the "extended" XMega jumps.
 420  * + It also doesn't check whether the core it's
 421  *   emulating is supposed to have the fancy instructions, like multiply and such.
 422  *
 423  * for now all instructions take "one" cycle, the cycle+=<extra> needs to be added.
 424  */
 425 uint16_t avr_run_one(avr_t * avr)
 426 {
 427 #if CONFIG_SIMAVR_TRACE
 428         /*
 429          * this traces spurious reset or bad jumps
 430          */
 431         if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
 432                 avr->trace = 1;
 433                 STATE("RESET\n");
 434                 CRASH();
 435         }
 436         avr->touched[0] = avr->touched[1] = avr->touched[2] = 0;
 437 #endif
 438
 439         uint32_t        opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
 440         uint32_t        new_pc = avr->pc + 2;   // future "default" pc
 441         int             cycle = 1;
 442
 443         switch (opcode & 0xf000) {
 444                 case 0x0000: {
 445                         switch (opcode) {
 446                                 case 0x0000: {  // NOP
 447                                         STATE("nop\n");
 448                                 }       break;
 449                                 default: {
 450                                         switch (opcode & 0xfc00) {
 451                                                 case 0x0400: {  // CPC compare with carry 0000 01rd dddd rrrr
 452                                                         get_r_d_10(opcode);
 453                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 454                                                         STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 455                                                         if (res)
 456                                                                 avr->sreg[S_Z] = 0;
 457                                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 458                                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 459                                                         avr->sreg[S_N] = (res >> 7) & 1;
 460                                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 461                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 462                                                         SREG();
 463                                                 }       break;
 464                                                 case 0x0c00: {  // ADD without carry 0000 11 rd dddd rrrr
 465                                                         get_r_d_10(opcode);
 466                                                         uint8_t res = vd + vr;
 467                                                         if (r == d) {
 468                                                                 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
 469                                                         } else {
 470                                                                 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 471                                                         }
 472                                                         _avr_set_r(avr, d, res);
 473                                                         avr->sreg[S_Z] = res == 0;
 474                                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 475                                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 476                                                         avr->sreg[S_N] = (res >> 7) & 1;
 477                                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 478                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 479                                                         SREG();
 480                                                 }       break;
 481                                                 case 0x0800: {  // SBC substract with carry 0000 10rd dddd rrrr
 482                                                         get_r_d_10(opcode);
 483                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 484                                                         STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 485                                                         _avr_set_r(avr, d, res);
 486                                                         if (res)
 487                                                                 avr->sreg[S_Z] = 0;
 488                                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 489                                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 490                                                         avr->sreg[S_N] = (res >> 7) & 1;
 491                                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 492                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 493                                                         SREG();
 494                                                 }       break;
 495                                                 default:
 496                                                         switch (opcode & 0xff00) {
 497                                                                 case 0x0100: {  // MOVW – Copy Register Word 0000 0001 dddd rrrr
 498                                                                         uint8_t d = ((opcode >> 4) & 0xf) << 1;
 499                                                                         uint8_t r = ((opcode) & 0xf) << 1;
 500                                                                         STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
 501                                                                         _avr_set_r(avr, d, avr->data[r]);
 502                                                                         _avr_set_r(avr, d+1, avr->data[r+1]);
 503                                                                 }       break;
 504                                                                 case 0x0200: {  // MULS – Multiply Signed 0000 0010 dddd rrrr
 505                                                                         int8_t r = opcode & 0xf;
 506                                                                         int8_t d = (opcode >> 4) & 0xf;
 507                                                                         int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 508                                                                         STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 509                                                                         _avr_set_r(avr, 0, res);
 510                                                                         _avr_set_r(avr, 1, res >> 8);
 511                                                                         avr->sreg[S_C] = (res >> 15) & 1;
 512                                                                         avr->sreg[S_Z] = res == 0;
 513                                                                         SREG();
 514                                                                 }       break;
 515                                                                 case 0x0300: {  // multiplications
 516                                                                         int8_t r = 16 + (opcode & 0x7);
 517                                                                         int8_t d = 16 + ((opcode >> 4) & 0x7);
 518                                                                         int16_t res = 0;
 519                                                                         uint8_t c = 0;
 520                                                                         const char * name = "";
 521                                                                         switch (opcode & 0x88) {
 522                                                                                 case 0x00:      // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
 523                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 524                                                                                         c = (res >> 15) & 1;
 525                                                                                         name = "mulsu";
 526                                                                                         break;
 527                                                                                 case 0x08:      // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
 528                                                                                         res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
 529                                                                                         c = (res >> 15) & 1;
 530                                                                                         res <<= 1;
 531                                                                                         name = "fmul";
 532                                                                                         break;
 533                                                                                 case 0x80:      // FMULS – Multiply Signed  0000 0011 1ddd 0rrr
 534                                                                                         res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 535                                                                                         c = (res >> 15) & 1;
 536                                                                                         res <<= 1;
 537                                                                                         name = "fmuls";
 538                                                                                         break;
 539                                                                                 case 0x88:      // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 0rrr
 540                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 541                                                                                         c = (res >> 15) & 1;
 542                                                                                         res <<= 1;
 543                                                                                         name = "fmulsu";
 544                                                                                         break;
 545                                                                         }
 546                                                                         cycle++;
 547                                                                         STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 548                                                                         _avr_set_r(avr, 0, res);
 549                                                                         _avr_set_r(avr, 1, res >> 8);
 550                                                                         avr->sreg[S_C] = c;
 551                                                                         avr->sreg[S_Z] = res == 0;
 552                                                                         SREG();
 553                                                                 }       break;
 554                                                                 default: _avr_invalid_opcode(avr);
 555                                                         }
 556                                         }
 557                                 }
 558                         }
 559                 }       break;
 560
 561                 case 0x1000: {
 562                         switch (opcode & 0xfc00) {
 563                                 case 0x1800: {  // SUB without carry 0000 10 rd dddd rrrr
 564                                         get_r_d_10(opcode);
 565                                         uint8_t res = vd - vr;
 566                                         STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 567                                         _avr_set_r(avr, d, res);
 568                                         avr->sreg[S_Z] = res == 0;
 569                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 570                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 571                                         avr->sreg[S_N] = (res >> 7) & 1;
 572                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 573                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 574                                         SREG();
 575                                 }       break;
 576                                 case 0x1000: {  // CPSE Compare, skip if equal 0000 10 rd dddd rrrr
 577                                         get_r_d_10(opcode);
 578                                         uint16_t res = vd == vr;
 579                                         STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":"not ");
 580                                         if (res) {
 581                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
 582                                                         new_pc += 4; cycle += 2;
 583                                                 } else {
 584                                                         new_pc += 2; cycle++;
 585                                                 }
 586                                         }
 587                                 }       break;
 588                                 case 0x1400: {  // CP Compare 0000 10 rd dddd rrrr
 589                                         get_r_d_10(opcode);
 590                                         uint8_t res = vd - vr;
 591                                         STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 592                                         avr->sreg[S_Z] = res == 0;
 593                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 594                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 595                                         avr->sreg[S_N] = res >> 7;
 596                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 597                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 598                                         SREG();
 599                                 }       break;
 600                                 case 0x1c00: {  // ADD with carry 0001 11 rd dddd rrrr
 601                                         get_r_d_10(opcode);
 602                                         uint8_t res = vd + vr + avr->sreg[S_C];
 603                                         if (r == d) {
 604                                                 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
 605                                         } else {
 606                                                 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 607                                         }
 608                                         _avr_set_r(avr, d, res);
 609                                         avr->sreg[S_Z] = res == 0;
 610                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 611                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 612                                         avr->sreg[S_N] = (res >> 7) & 1;
 613                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 614                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 615                                         SREG();
 616                                 }       break;
 617                                 default: _avr_invalid_opcode(avr);
 618                         }
 619                 }       break;
 620
 621                 case 0x2000: {
 622                         switch (opcode & 0xfc00) {
 623                                 case 0x2000: {  // AND  0010 00rd dddd rrrr
 624                                         get_r_d_10(opcode);
 625                                         uint8_t res = vd & vr;
 626                                         if (r == d) {
 627                                                 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
 628                                         } else {
 629                                                 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 630                                         }
 631                                         _avr_set_r(avr, d, res);
 632                                         avr->sreg[S_Z] = res == 0;
 633                                         avr->sreg[S_N] = (res >> 7) & 1;
 634                                         avr->sreg[S_V] = 0;
 635                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 636                                         SREG();
 637                                 }       break;
 638                                 case 0x2400: {  // EOR  0010 01rd dddd rrrr
 639                                         get_r_d_10(opcode);
 640                                         uint8_t res = vd ^ vr;
 641                                         if (r==d) {
 642                                                 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
 643                                         } else {
 644                                                 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 645                                         }
 646                                         _avr_set_r(avr, d, res);
 647                                         avr->sreg[S_Z] = res == 0;
 648                                         avr->sreg[S_N] = (res >> 7) & 1;
 649                                         avr->sreg[S_V] = 0;
 650                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 651                                         SREG();
 652                                 }       break;
 653                                 case 0x2800: {  // OR Logical OR        0010 10rd dddd rrrr
 654                                         get_r_d_10(opcode);
 655                                         uint8_t res = vd | vr;
 656                                         STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 657                                         _avr_set_r(avr, d, res);
 658                                         avr->sreg[S_Z] = res == 0;
 659                                         avr->sreg[S_N] = (res >> 7) & 1;
 660                                         avr->sreg[S_V] = 0;
 661                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 662                                         SREG();
 663                                 }       break;
 664                                 case 0x2c00: {  // MOV  0010 11rd dddd rrrr
 665                                         get_r_d_10(opcode);
 666                                         uint8_t res = vr;
 667                                         STATE("mov %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 668                                         _avr_set_r(avr, d, res);
 669                                 }       break;
 670                                 default: _avr_invalid_opcode(avr);
 671                         }
 672                 }       break;
 673
 674                 case 0x3000: {  // CPI 0011 KKKK rrrr KKKK
 675                         get_k_r16(opcode);
 676                         uint8_t vr = avr->data[r];
 677                         uint8_t res = vr - k;
 678                         STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
 679
 680                         avr->sreg[S_Z] = res == 0;
 681                         avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
 682                         avr->sreg[S_V] = get_compare_overflow(res, vr, k);
 683                         avr->sreg[S_N] = (res >> 7) & 1;
 684                         avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
 685                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 686                         SREG();
 687                 }       break;
 688
 689                 case 0x4000: {  // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
 690                         get_k_r16(opcode);
 691                         uint8_t vr = avr->data[r];
 692                         uint8_t res = vr - k - avr->sreg[S_C];
 693                         STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 694                         _avr_set_r(avr, r, res);
 695                         avr->sreg[S_Z] = res  == 0;
 696                         avr->sreg[S_N] = (res >> 7) & 1;
 697                         avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
 698                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 699                         SREG();
 700                 }       break;
 701
 702                 case 0x5000: {  // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
 703                         get_k_r16(opcode);
 704                         uint8_t vr = avr->data[r];
 705                         uint8_t res = vr - k;
 706                         STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 707                         _avr_set_r(avr, r, res);
 708                         avr->sreg[S_Z] = res  == 0;
 709                         avr->sreg[S_N] = (res >> 7) & 1;
 710                         avr->sreg[S_C] = k > vr;
 711                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 712                         SREG();
 713                 }       break;
 714
 715                 case 0x6000: {  // ORI aka SBR  Logical AND with Immediate      0110 kkkk dddd kkkk
 716                         get_k_r16(opcode);
 717                         uint8_t res = avr->data[r] | k;
 718                         STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 719                         _avr_set_r(avr, r, res);
 720                         avr->sreg[S_Z] = res == 0;
 721                         avr->sreg[S_N] = (res >> 7) & 1;
 722                         avr->sreg[S_V] = 0;
 723                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 724                         SREG();
 725                 }       break;
 726
 727                 case 0x7000: {  // ANDI Logical AND with Immediate      0111 kkkk dddd kkkk
 728                         get_k_r16(opcode);
 729                         uint8_t res = avr->data[r] & k;
 730                         STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 731                         _avr_set_r(avr, r, res);
 732                         avr->sreg[S_Z] = res == 0;
 733                         avr->sreg[S_N] = (res >> 7) & 1;
 734                         avr->sreg[S_V] = 0;
 735                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 736                         SREG();
 737                 }       break;
 738
 739                 case 0xa000:
 740                 case 0x8000: {
 741                         switch (opcode & 0xd008) {
 742                                 case 0xa000:
 743                                 case 0x8000: {  // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
 744                                         uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 745                                         uint8_t r = (opcode >> 4) & 0x1f;
 746                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 747
 748                                         if (opcode & 0x0200) {
 749                                                 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 750                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 751                                         } else {
 752                                                 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 753                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 754                                         }
 755                                         cycle += 2;
 756                                 }       break;
 757                                 case 0xa008:
 758                                 case 0x8008: {  // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
 759                                         uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
 760                                         uint8_t r = (opcode >> 4) & 0x1f;
 761                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 762
 763                                         if (opcode & 0x0200) {
 764                                                 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 765                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 766                                         } else {
 767                                                 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 768                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 769                                         }
 770                                         cycle += 2;
 771                                 }       break;
 772                                 default: _avr_invalid_opcode(avr);
 773                         }
 774                 }       break;
 775
 776                 case 0x9000: {
 777                         /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
 778                         if ((opcode & 0xff0f) == 0x9408) {
 779                                 uint8_t b = (opcode >> 4) & 7;
 780                                 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
 781                                 avr->sreg[b] = (opcode & 0x0080) == 0;
 782                                 SREG();
 783                         } else switch (opcode) {
 784                                 case 0x9588: { // SLEEP
 785                                         STATE("sleep\n");
 786                                         avr->state = cpu_Sleeping;
 787                                 }       break;
 788                                 case 0x9598: { // BREAK
 789                                         STATE("break\n");
 790                                         if (avr->gdb) {
 791                                                 // if gdb is on, we break here as in here
 792                                                 // and we do so until gdb restores the instruction
 793                                                 // that was here before
 794                                                 avr->state = cpu_StepDone;
 795                                                 new_pc = avr->pc;
 796                                                 cycle = 0;
 797                                         }
 798                                 }       break;
 799                                 case 0x95a8: { // WDR
 800                                         STATE("wdr\n");
 801                                 }       break;
 802                                 case 0x95e8: { // SPM
 803                                         STATE("spm\n");
 804                                         avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
 805                                 }       break;
 806                                 case 0x9409: { // IJMP Indirect jump
 807                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 808                                         STATE("ijmp Z[%04x]\n", z << 1);
 809                                         new_pc = z << 1;
 810                                         cycle++;
 811                                         TRACE_JUMP();
 812                                 }       break;
 813                                 case 0x9509: { // ICALL Indirect Call to Subroutine
 814                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 815                                         STATE("icall Z[%04x]\n", z << 1);
 816                                         _avr_push16(avr, new_pc >> 1);
 817                                         new_pc = z << 1;
 818                                         cycle += 2;
 819                                         TRACE_JUMP();
 820                                         STACK_FRAME_PUSH();
 821                                 }       break;
 822                                 case 0x9518:    // RETI
 823                                 case 0x9508: {  // RET
 824                                         new_pc = _avr_pop16(avr) << 1;
 825                                         if (opcode & 0x10)      // reti
 826                                                 avr->sreg[S_I] = 1;
 827                                         cycle += 3;
 828                                         STATE("ret%s\n", opcode & 0x10 ? "i" : "");
 829                                         TRACE_JUMP();
 830                                         STACK_FRAME_POP();
 831                                 }       break;
 832                                 case 0x95c8: {  // LPM Load Program Memory R0 <- (Z)
 833                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 834                                         STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
 835                                         _avr_set_r(avr, 0, avr->flash[z]);
 836                                 }       break;
 837                                 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
 838                                 case 0x9478:
 839                                 {       // BSET 1001 0100 0ddd 1000
 840                                         uint8_t b = (opcode >> 4) & 7;
 841                                         avr->sreg[b] = 1;
 842                                         STATE("bset %c\n", _sreg_bit_name[b]);
 843                                         SREG();
 844                                 }       break;
 845                                 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
 846                                 case 0x94f8:
 847                                 {       // BSET 1001 0100 0ddd 1000
 848                                         uint8_t b = (opcode >> 4) & 7;
 849                                         avr->sreg[b] = 0;
 850                                         STATE("bclr %c\n", _sreg_bit_name[b]);
 851                                         SREG();
 852                                 }       break;
 853                                 default:  {
 854                                         switch (opcode & 0xfe0f) {
 855                                                 case 0x9000: {  // LDS Load Direct from Data Space, 32 bits
 856                                                         uint8_t r = (opcode >> 4) & 0x1f;
 857                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 858                                                         new_pc += 2;
 859                                                         STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
 860                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 861                                                         cycle++;
 862                                                 }       break;
 863                                                 case 0x9005:
 864                                                 case 0x9004: {  // LPM Load Program Memory 1001 000d dddd 01oo
 865                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 866                                                         uint8_t r = (opcode >> 4) & 0x1f;
 867                                                         int op = opcode & 3;
 868                                                         STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
 869                                                         _avr_set_r(avr, r, avr->flash[z]);
 870                                                         if (op == 1) {
 871                                                                 z++;
 872                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 873                                                                 _avr_set_r(avr, R_ZL, z);
 874                                                         }
 875                                                         cycle += 2;
 876                                                 }       break;
 877                                                 case 0x900c:
 878                                                 case 0x900d:
 879                                                 case 0x900e: {  // LD Load Indirect from Data using X 1001 000r rrrr 11oo
 880                                                         int op = opcode & 3;
 881                                                         uint8_t r = (opcode >> 4) & 0x1f;
 882                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 883                                                         STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
 884
 885                                                         if (op == 2) x--;
 886                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 887                                                         if (op == 1) x++;
 888                                                         _avr_set_r(avr, R_XH, x >> 8);
 889                                                         _avr_set_r(avr, R_XL, x);
 890                                                 }       break;
 891                                                 case 0x920c:
 892                                                 case 0x920d:
 893                                                 case 0x920e: {  // ST Store Indirect Data Space X 1001 001r rrrr 11oo
 894                                                         int op = opcode & 3;
 895                                                         uint8_t r = (opcode >> 4) & 0x1f;
 896                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 897                                                         STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 898                                                         cycle++;
 899                                                         if (op == 2) x--;
 900                                                         _avr_set_ram(avr, x, avr->data[r]);
 901                                                         if (op == 1) x++;
 902                                                         _avr_set_r(avr, R_XH, x >> 8);
 903                                                         _avr_set_r(avr, R_XL, x);
 904                                                 }       break;
 905                                                 case 0x9009:
 906                                                 case 0x900a: {  // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
 907                                                         int op = opcode & 3;
 908                                                         uint8_t r = (opcode >> 4) & 0x1f;
 909                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 910                                                         STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
 911                                                         cycle++;
 912                                                         if (op == 2) y--;
 913                                                         _avr_set_r(avr, r, _avr_get_ram(avr, y));
 914                                                         if (op == 1) y++;
 915                                                         _avr_set_r(avr, R_YH, y >> 8);
 916                                                         _avr_set_r(avr, R_YL, y);
 917                                                 }       break;
 918                                                 case 0x9209:
 919                                                 case 0x920a: {  // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
 920                                                         int op = opcode & 3;
 921                                                         uint8_t r = (opcode >> 4) & 0x1f;
 922                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 923                                                         STATE("st %sY[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 924                                                         cycle++;
 925                                                         if (op == 2) y--;
 926                                                         _avr_set_ram(avr, y, avr->data[r]);
 927                                                         if (op == 1) y++;
 928                                                         _avr_set_r(avr, R_YH, y >> 8);
 929                                                         _avr_set_r(avr, R_YL, y);
 930                                                 }       break;
 931                                                 case 0x9200: {  // STS ! Store Direct to Data Space, 32 bits
 932                                                         uint8_t r = (opcode >> 4) & 0x1f;
 933                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 934                                                         new_pc += 2;
 935                                                         STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
 936                                                         _avr_set_ram(avr, x, avr->data[r]);
 937                                                 }       break;
 938                                                 case 0x9001:
 939                                                 case 0x9002: {  // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
 940                                                         int op = opcode & 3;
 941                                                         uint8_t r = (opcode >> 4) & 0x1f;
 942                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
 943                                                         STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
 944                                                         if (op == 2) z--;
 945                                                         _avr_set_r(avr, r, _avr_get_ram(avr, z));
 946                                                         if (op == 1) z++;
 947                                                         _avr_set_r(avr, R_ZH, z >> 8);
 948                                                         _avr_set_r(avr, R_ZL, z);
 949                                                 }       break;
 950                                                 case 0x9201:
 951                                                 case 0x9202: {  // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
 952                                                         int op = opcode & 3;
 953                                                         uint8_t r = (opcode >> 4) & 0x1f;
 954                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
 955                                                         STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 956                                                         if (op == 2) z--;
 957                                                         _avr_set_ram(avr, z, avr->data[r]);
 958                                                         if (op == 1) z++;
 959                                                         _avr_set_r(avr, R_ZH, z >> 8);
 960                                                         _avr_set_r(avr, R_ZL, z);
 961                                                 }       break;
 962                                                 case 0x900f: {  // POP 1001 000d dddd 1111
 963                                                         uint8_t r = (opcode >> 4) & 0x1f;
 964                                                         _avr_set_r(avr, r, _avr_pop8(avr));
 965                                                         uint16_t sp = _avr_sp_get(avr);
 966                                                         STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
 967                                                         cycle++;
 968                                                 }       break;
 969                                                 case 0x920f: {  // PUSH 1001 001d dddd 1111
 970                                                         uint8_t r = (opcode >> 4) & 0x1f;
 971                                                         _avr_push8(avr, avr->data[r]);
 972                                                         uint16_t sp = _avr_sp_get(avr);
 973                                                         STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
 974                                                         cycle++;
 975                                                 }       break;
 976                                                 case 0x9400: {  // COM – One’s Complement
 977                                                         uint8_t r = (opcode >> 4) & 0x1f;
 978                                                         uint8_t res = 0xff - avr->data[r];
 979                                                         STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
 980                                                         _avr_set_r(avr, r, res);
 981                                                         avr->sreg[S_Z] = res == 0;
 982                                                         avr->sreg[S_N] = res >> 7;
 983                                                         avr->sreg[S_V] = 0;
 984                                                         avr->sreg[S_C] = 1;
 985                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 986                                                         SREG();
 987                                                 }       break;
 988                                                 case 0x9401: {  // NEG – One’s Complement
 989                                                         uint8_t r = (opcode >> 4) & 0x1f;
 990                                                         uint8_t rd = avr->data[r];
 991                                                         uint8_t res = 0x00 - rd;
 992                                                         STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
 993                                                         _avr_set_r(avr, r, res);
 994                                                         avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
 995                                                         avr->sreg[S_Z] = res == 0;
 996                                                         avr->sreg[S_N] = res >> 7;
 997                                                         avr->sreg[S_V] = res == 0x80;
 998                                                         avr->sreg[S_C] = res != 0;
 999                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1000                                                         SREG();
1001                                                 }       break;
1002                                                 case 0x9402: {  // SWAP – Swap Nibbles
1003                                                         uint8_t r = (opcode >> 4) & 0x1f;
1004                                                         uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1005                                                         STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1006                                                         _avr_set_r(avr, r, res);
1007                                                 }       break;
1008                                                 case 0x9403: {  // INC – Increment
1009                                                         uint8_t r = (opcode >> 4) & 0x1f;
1010                                                         uint8_t res = avr->data[r] + 1;
1011                                                         STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1012                                                         _avr_set_r(avr, r, res);
1013                                                         avr->sreg[S_Z] = res == 0;
1014                                                         avr->sreg[S_N] = res >> 7;
1015                                                         avr->sreg[S_V] = res == 0x7f;
1016                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1017                                                         SREG();
1018                                                 }       break;
1019                                                 case 0x9405: {  // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1020                                                         uint8_t r = (opcode >> 4) & 0x1f;
1021                                                         uint8_t vr = avr->data[r];
1022                                                         uint8_t res = (vr >> 1) | (vr & 0x80);
1023                                                         STATE("asr %s[%02x]\n", avr_regname(r), vr);
1024                                                         _avr_set_r(avr, r, res);
1025                                                         avr->sreg[S_Z] = res == 0;
1026                                                         avr->sreg[S_C] = vr & 1;
1027                                                         avr->sreg[S_N] = res >> 7;
1028                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1029                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1030                                                         SREG();
1031                                                 }       break;
1032                                                 case 0x9406: {  // LSR 1001 010d dddd 0110
1033                                                         uint8_t r = (opcode >> 4) & 0x1f;
1034                                                         uint8_t vr = avr->data[r];
1035                                                         uint8_t res = vr >> 1;
1036                                                         STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1037                                                         _avr_set_r(avr, r, res);
1038                                                         avr->sreg[S_Z] = res == 0;
1039                                                         avr->sreg[S_C] = vr & 1;
1040                                                         avr->sreg[S_N] = 0;
1041                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1042                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1043                                                         SREG();
1044                                                 }       break;
1045                                                 case 0x9407: {  // ROR 1001 010d dddd 0111
1046                                                         uint8_t r = (opcode >> 4) & 0x1f;
1047                                                         uint8_t vr = avr->data[r];
1048                                                         uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1049                                                         STATE("ror %s[%02x]\n", avr_regname(r), vr);
1050                                                         _avr_set_r(avr, r, res);
1051                                                         avr->sreg[S_Z] = res == 0;
1052                                                         avr->sreg[S_C] = vr & 1;
1053                                                         avr->sreg[S_N] = 0;
1054                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1055                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1056                                                         SREG();
1057                                                 }       break;
1058                                                 case 0x940a: {  // DEC – Decrement
1059                                                         uint8_t r = (opcode >> 4) & 0x1f;
1060                                                         uint8_t res = avr->data[r] - 1;
1061                                                         STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1062                                                         _avr_set_r(avr, r, res);
1063                                                         avr->sreg[S_Z] = res == 0;
1064                                                         avr->sreg[S_N] = res >> 7;
1065                                                         avr->sreg[S_V] = res == 0x80;
1066                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1067                                                         SREG();
1068                                                 }       break;
1069                                                 case 0x940c:
1070                                                 case 0x940d: {  // JMP Long Call to sub, 32 bits
1071                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1072                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1073                                                         a = (a << 16) | x;
1074                                                         STATE("jmp 0x%06x\n", a);
1075                                                         new_pc = a << 1;
1076                                                         cycle += 2;
1077                                                         TRACE_JUMP();
1078                                                 }       break;
1079                                                 case 0x940e:
1080                                                 case 0x940f: {  // CALL Long Call to sub, 32 bits
1081                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1082                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1083                                                         a = (a << 16) | x;
1084                                                         STATE("call 0x%06x\n", a);
1085                                                         new_pc += 2;
1086                                                         _avr_push16(avr, new_pc >> 1);
1087                                                         new_pc = a << 1;
1088                                                         cycle += 3;     // 4 cycles
1089                                                         TRACE_JUMP();
1090                                                         STACK_FRAME_PUSH();
1091                                                 }       break;
1092
1093                                                 default: {
1094                                                         switch (opcode & 0xff00) {
1095                                                                 case 0x9600: {  // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1096                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1097                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1098                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1099                                                                         uint32_t res = rdl | (rdh << 8);
1100                                                                         STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1101                                                                         res += k;
1102                                                                         _avr_set_r(avr, r + 1, res >> 8);
1103                                                                         _avr_set_r(avr, r, res);
1104                                                                         avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1105                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1106                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1107                                                                         avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1108                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1109                                                                         SREG();
1110                                                                         cycle++;
1111                                                                 }       break;
1112                                                                 case 0x9700: {  // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1113                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1114                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1115                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1116                                                                         uint32_t res = rdl | (rdh << 8);
1117                                                                         STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1118                                                                         res -= k;
1119                                                                         _avr_set_r(avr, r + 1, res >> 8);
1120                                                                         _avr_set_r(avr, r, res);
1121                                                                         avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1122                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1123                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1124                                                                         avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1125                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1126                                                                         SREG();
1127                                                                         cycle++;
1128                                                                 }       break;
1129                                                                 case 0x9800: {  // CBI - Clear Bit in I/O Registe 1001 1000 AAAA Abbb
1130                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1131                                                                         uint8_t b = opcode & 0x7;
1132                                                                         uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1133                                                                         STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1134                                                                         _avr_set_ram(avr, io, res);
1135                                                                         cycle++;
1136                                                                 }       break;
1137                                                                 case 0x9900: {  // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1138                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1139                                                                         uint8_t b = opcode & 0x7;
1140                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1141                                                                         STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":"not ");
1142                                                                         if (!res) {
1143                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1144                                                                                         new_pc += 4; cycle += 2;
1145                                                                                 } else {
1146                                                                                         new_pc += 2; cycle++;
1147                                                                                 }
1148                                                                         }
1149                                                                 }       break;
1150                                                                 case 0x9a00: {  // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1151                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1152                                                                         uint8_t b = opcode & 0x7;
1153                                                                         uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1154                                                                         STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1155                                                                         _avr_set_ram(avr, io, res);
1156                                                                         cycle++;
1157                                                                 }       break;
1158                                                                 case 0x9b00: {  // SBIS - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1159                                                                         uint8_t io = (opcode >> 3) & 0x1f;
1160                                                                         uint8_t b = opcode & 0x7;
1161                                                                         uint8_t res = _avr_get_ram(avr, io + 32) & (1 << b);
1162                                                                         STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":"not ");
1163                                                                         if (res) {
1164                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1165                                                                                         new_pc += 4; cycle += 2;
1166                                                                                 } else {
1167                                                                                         new_pc += 2; cycle++;
1168                                                                                 }
1169                                                                         }
1170                                                                 }       break;
1171                                                                 default:
1172                                                                         switch (opcode & 0xfc00) {
1173                                                                                 case 0x9c00: {  // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1174                                                                                         get_r_d_10(opcode);
1175                                                                                         uint16_t res = vd * vr;
1176                                                                                         STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1177                                                                                         _avr_set_r(avr, 0, res);
1178                                                                                         _avr_set_r(avr, 1, res >> 8);
1179                                                                                         avr->sreg[S_Z] = res == 0;
1180                                                                                         avr->sreg[S_C] = (res >> 15) & 1;
1181                                                                                         SREG();
1182                                                                                 }       break;
1183                                                                                 default: _avr_invalid_opcode(avr);
1184                                                                         }
1185                                                         }
1186                                                 }       break;
1187                                         }
1188                                 }       break;
1189                         }
1190                 }       break;
1191
1192                 case 0xb000: {
1193                         switch (opcode & 0xf800) {
1194                                 case 0xb800: {  // OUT A,Rr 1011 1AAr rrrr AAAA
1195                                         uint8_t r = (opcode >> 4) & 0x1f;
1196                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1197                                         STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1198                                         // todo: store to IO register
1199                                         _avr_set_ram(avr, A, avr->data[r]);
1200                                 //      avr->data[A] = ;
1201                                 }       break;
1202                                 case 0xb000: {  // IN Rd,A 1011 0AAr rrrr AAAA
1203                                         uint8_t r = (opcode >> 4) & 0x1f;
1204                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1205                                         STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1206                                         // todo: get the IO register
1207                                         _avr_set_r(avr, r, _avr_get_ram(avr, A));
1208                                 }       break;
1209                                 default: _avr_invalid_opcode(avr);
1210                         }
1211                 }       break;
1212
1213                 case 0xc000: {
1214                         // RJMP 1100 kkkk kkkk kkkk
1215                         short o = ((short)(opcode << 4)) >> 4;
1216                         STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1217                         new_pc = new_pc + (o << 1);
1218                         cycle++;
1219                         TRACE_JUMP();
1220                 }       break;
1221
1222                 case 0xd000: {
1223                         // RCALL 1100 kkkk kkkk kkkk
1224                         short o = ((short)(opcode << 4)) >> 4;
1225                         STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1226                         _avr_push16(avr, new_pc >> 1);
1227                         new_pc = new_pc + (o << 1);
1228                         cycle += 2;
1229                         // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1230                         if (o != 0) {
1231                                 TRACE_JUMP();
1232                                 STACK_FRAME_PUSH();
1233                         }
1234                 }       break;
1235
1236                 case 0xe000: {  // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1237                         uint8_t d = 16 + ((opcode >> 4) & 0xf);
1238                         uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1239                         STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1240                         _avr_set_r(avr, d, k);
1241                 }       break;
1242
1243                 case 0xf000: {
1244                         switch (opcode & 0xfe00) {
1245                                 case 0xf000:
1246                                 case 0xf200:
1247                                 case 0xf400:
1248                                 case 0xf600: {  // All the SREG branches
1249                                         short o = ((short)(opcode << 6)) >> 9; // offset
1250                                         uint8_t s = opcode & 7;
1251                                         int set = (opcode & 0x0400) == 0;               // this bit means BRXC otherwise BRXS
1252                                         int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1253                                         const char *names[2][8] = {
1254                                                         { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1255                                                         { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1256                                         };
1257                                         if (names[set][s]) {
1258                                                 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1259                                         } else {
1260                                                 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1261                                         }
1262                                         if (branch) {
1263                                                 cycle++;
1264                                                 new_pc = new_pc + (o << 1);
1265                                         }
1266                                 }       break;
1267                                 case 0xf800:
1268                                 case 0xf900: {  // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1269                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1270                                         uint8_t s = opcode & 7;
1271                                         uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1272                                         STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1273                                         _avr_set_r(avr, r, v);
1274                                 }       break;
1275                                 case 0xfa00:
1276                                 case 0xfb00:{   // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1277                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1278                                         uint8_t s = opcode & 7;
1279                                         STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1280                                         avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1281                                         SREG();
1282                                 }       break;
1283                                 case 0xfc00:
1284                                 case 0xfe00: {  // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1285                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1286                                         uint8_t s = opcode & 7;
1287                                         int set = (opcode & 0x0200) != 0;
1288                                         int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1289                                         STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1290                                         if (branch)
1291                                                 new_pc = new_pc + 2;
1292                                 }       break;
1293                                 default: _avr_invalid_opcode(avr);
1294                         }
1295                 }       break;
1296
1297                 default: _avr_invalid_opcode(avr);
1298
1299         }
1300         avr->cycle += cycle;
1301         return new_pc;
1302 }
1303
1304