git.rot13.org Git - simavr/blob - simavr/sim/sim_core.c

   1 /*
   2         sim_core.c
   3
   4         Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
   5
   6         This file is part of simavr.
   7
   8         simavr is free software: you can redistribute it and/or modify
   9         it under the terms of the GNU General Public License as published by
  10         the Free Software Foundation, either version 3 of the License, or
  11         (at your option) any later version.
  12
  13         simavr is distributed in the hope that it will be useful,
  14         but WITHOUT ANY WARRANTY; without even the implied warranty of
  15         MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16         GNU General Public License for more details.
  17
  18         You should have received a copy of the GNU General Public License
  19         along with simavr.  If not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include <stdlib.h>
  23 #include <stdio.h>
  24 #include <string.h>
  25 #include <ctype.h>
  26 #include "sim_avr.h"
  27 #include "sim_core.h"
  28 #include "avr_flash.h"
  29 #include "avr_watchdog.h"
  30
  31 // SREG bit names
  32 const char * _sreg_bit_name = "cznvshti";
  33
  34 /*
  35  * Handle "touching" registers, marking them changed.
  36  * This is used only for debugging purposes to be able to
  37  * print the effects of each instructions on registers
  38  */
  39 #if CONFIG_SIMAVR_TRACE
  40 #define REG_TOUCH(a, r) (a)->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
  41 #define REG_ISTOUCHED(a, r) ((a)->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
  42
  43 /*
  44  * This allows a "special case" to skip indtruction tracing when in these
  45  * symbols. since printf() is useful to have, but generates a lot of cycles
  46  */
  47 int dont_trace(const char * name)
  48 {
  49         return (
  50                 !strcmp(name, "uart_putchar") ||
  51                 !strcmp(name, "fputc") ||
  52                 !strcmp(name, "printf") ||
  53                 !strcmp(name, "vfprintf") ||
  54                 !strcmp(name, "__ultoa_invert") ||
  55                 !strcmp(name, "__prologue_saves__") ||
  56                 !strcmp(name, "__epilogue_restores__"));
  57 }
  58
  59 int donttrace = 0;
  60
  61 #define STATE(_f, args...) { \
  62         if (avr->trace) {\
  63                 if (avr->codeline && avr->codeline[avr->pc>>1]) {\
  64                         const char * symn = avr->codeline[avr->pc>>1]->symbol; \
  65                         int dont = 0 && dont_trace(symn);\
  66                         if (dont!=donttrace) { \
  67                                 donttrace = dont;\
  68                                 DUMP_REG();\
  69                         }\
  70                         if (donttrace==0)\
  71                                 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
  72                 } else \
  73                         printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
  74                 }\
  75         }
  76 #define SREG() if (avr->trace && donttrace == 0) {\
  77         printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
  78         for (int _sbi = 0; _sbi < 8; _sbi++)\
  79                 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
  80         printf("\n");\
  81 }
  82 #else
  83 #define REG_TOUCH(a, r)
  84 #define STATE(_f, args...)
  85 #define SREG()
  86 #endif
  87
  88 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
  89 {
  90         if (addr > avr->ramend) {
  91                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
  92                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  93                 CRASH();
  94         }
  95         if (addr < 32) {
  96                 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
  97                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
  98                 CRASH();
  99         }
 100 #if AVR_STACK_WATCH
 101         /*
 102          * this checks that the current "function" is not doctoring the stack frame that is located
 103          * higher on the stack than it should be. It's a sign of code that has overrun it's stack
 104          * frame and is munching on it's own return address.
 105          */
 106         if (avr->stack_frame_index > 1 && addr > avr->stack_frame[avr->stack_frame_index-2].sp) {
 107                 printf("\e[31m%04x : munching stack SP %04x, A=%04x <= %02x\e[0m\n", avr->pc, _avr_sp_get(avr), addr, v);
 108         }
 109 #endif
 110         avr->data[addr] = v;
 111 }
 112
 113 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
 114 {
 115         if (addr > avr->ramend) {
 116                 printf("*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n",
 117                                 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
 118                 CRASH();
 119         }
 120         return avr->data[addr];
 121 }
 122
 123 /*
 124  * Set a register (r < 256)
 125  * if it's an IO regisrer (> 31) also (try to) call any callback that was
 126  * registered to track changes to that register.
 127  */
 128 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
 129 {
 130         REG_TOUCH(avr, r);
 131
 132         if (r == R_SREG) {
 133                 avr->data[R_SREG] = v;
 134                 // unsplit the SREG
 135                 for (int i = 0; i < 8; i++)
 136                         avr->sreg[i] = (v & (1 << i)) != 0;
 137                 SREG();
 138         }
 139         if (r > 31) {
 140                 uint8_t io = AVR_DATA_TO_IO(r);
 141                 if (avr->io[io].w.c)
 142                         avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
 143                 else
 144                         avr->data[r] = v;
 145                 if (avr->io[io].irq) {
 146                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 147                         for (int i = 0; i < 8; i++)
 148                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 149                 }
 150         } else
 151                 avr->data[r] = v;
 152 }
 153
 154 /*
 155  * Stack pointer access
 156  */
 157 inline uint16_t _avr_sp_get(avr_t * avr)
 158 {
 159         return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
 160 }
 161
 162 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
 163 {
 164         _avr_set_r(avr, R_SPL, sp);
 165         _avr_set_r(avr, R_SPH, sp >> 8);
 166 }
 167
 168 /*
 169  * Set any address to a value; split between registers and SRAM
 170  */
 171 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
 172 {
 173         if (addr < 256)
 174                 _avr_set_r(avr, addr, v);
 175         else
 176                 avr_core_watch_write(avr, addr, v);
 177 }
 178
 179 /*
 180  * Get a value from SRAM.
 181  */
 182 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
 183 {
 184         if (addr == R_SREG) {
 185                 /*
 186                  * SREG is special it's reconstructed when read
 187                  * while the core itself uses the "shortcut" array
 188                  */
 189                 avr->data[R_SREG] = 0;
 190                 for (int i = 0; i < 8; i++)
 191                         if (avr->sreg[i] > 1) {
 192                                 printf("** Invalid SREG!!\n");
 193                                 CRASH();
 194                         } else if (avr->sreg[i])
 195                                 avr->data[R_SREG] |= (1 << i);
 196
 197         } else if (addr > 31 && addr < 256) {
 198                 uint8_t io = AVR_DATA_TO_IO(addr);
 199
 200                 if (avr->io[io].r.c)
 201                         avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
 202
 203                 if (avr->io[io].irq) {
 204                         uint8_t v = avr->data[addr];
 205                         avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
 206                         for (int i = 0; i < 8; i++)
 207                                 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
 208                 }
 209         }
 210         return avr_core_watch_read(avr, addr);
 211 }
 212
 213 /*
 214  * Stack push accessors. Push/pop 8 and 16 bits
 215  */
 216 static inline void _avr_push8(avr_t * avr, uint16_t v)
 217 {
 218         uint16_t sp = _avr_sp_get(avr);
 219         _avr_set_ram(avr, sp, v);
 220         _avr_sp_set(avr, sp-1);
 221 }
 222
 223 static inline uint8_t _avr_pop8(avr_t * avr)
 224 {
 225         uint16_t sp = _avr_sp_get(avr) + 1;
 226         uint8_t res = _avr_get_ram(avr, sp);
 227         _avr_sp_set(avr, sp);
 228         return res;
 229 }
 230
 231 inline void _avr_push16(avr_t * avr, uint16_t v)
 232 {
 233         _avr_push8(avr, v);
 234         _avr_push8(avr, v >> 8);
 235 }
 236
 237 static inline uint16_t _avr_pop16(avr_t * avr)
 238 {
 239         uint16_t res = _avr_pop8(avr) << 8;
 240         res |= _avr_pop8(avr);
 241         return res;
 242 }
 243
 244 /*
 245  * "Pretty" register names
 246  */
 247 const char * reg_names[255] = {
 248                 [R_XH] = "XH", [R_XL] = "XL",
 249                 [R_YH] = "YH", [R_YL] = "YL",
 250                 [R_ZH] = "ZH", [R_ZL] = "ZL",
 251                 [R_SPH] = "SPH", [R_SPL] = "SPL",
 252                 [R_SREG] = "SREG",
 253 };
 254
 255
 256 const char * avr_regname(uint8_t reg)
 257 {
 258         if (!reg_names[reg]) {
 259                 char tt[16];
 260                 if (reg < 32)
 261                         sprintf(tt, "r%d", reg);
 262                 else
 263                         sprintf(tt, "io:%02x", reg);
 264                 reg_names[reg] = strdup(tt);
 265         }
 266         return reg_names[reg];
 267 }
 268
 269 /*
 270  * Called when an invalid opcode is decoded
 271  */
 272 static void _avr_invalid_opcode(avr_t * avr)
 273 {
 274 #if CONFIG_SIMAVR_TRACE
 275         printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n",
 276                         avr->pc, avr->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 277 #else
 278         printf("\e[31m*** %04x: Invalid Opcode SP=%04x O=%04x \e[0m\n",
 279                         avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
 280 #endif
 281 }
 282
 283 #if CONFIG_SIMAVR_TRACE
 284 /*
 285  * Dump changed registers when tracing
 286  */
 287 void avr_dump_state(avr_t * avr)
 288 {
 289         if (!avr->trace || donttrace)
 290                 return;
 291
 292         int doit = 0;
 293
 294         for (int r = 0; r < 3 && !doit; r++)
 295                 if (avr->touched[r])
 296                         doit = 1;
 297         if (!doit)
 298                 return;
 299         printf("                                       ->> ");
 300         const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
 301         for (int i = 0; i < 4; i++)
 302                 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
 303                         REG_TOUCH(avr, r16[i]);
 304                         REG_TOUCH(avr, r16[i]+1);
 305                 }
 306
 307         for (int i = 0; i < 3*32; i++)
 308                 if (REG_ISTOUCHED(avr, i)) {
 309                         printf("%s=%02x ", avr_regname(i), avr->data[i]);
 310                 }
 311         printf("\n");
 312 }
 313 #endif
 314
 315 #define get_r_d_10(o) \
 316                 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
 317                 const uint8_t d = (o >> 4) & 0x1f;\
 318                 const uint8_t vd = avr->data[d], vr = avr->data[r];
 319 #define get_k_r16(o) \
 320                 const uint8_t r = 16 + ((o >> 4) & 0xf); \
 321                 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
 322
 323 /*
 324  * Add a "jump" address to the jump trace buffer
 325  */
 326 #if CONFIG_SIMAVR_TRACE
 327 #define TRACE_JUMP()\
 328         avr->old[avr->old_pci].pc = avr->pc;\
 329         avr->old[avr->old_pci].sp = _avr_sp_get(avr);\
 330         avr->old_pci = (avr->old_pci + 1) & (OLD_PC_SIZE-1);\
 331
 332 #if AVR_STACK_WATCH
 333 #define STACK_FRAME_PUSH()\
 334         avr->stack_frame[avr->stack_frame_index].pc = avr->pc;\
 335         avr->stack_frame[avr->stack_frame_index].sp = _avr_sp_get(avr);\
 336         avr->stack_frame_index++;
 337 #define STACK_FRAME_POP()\
 338         if (avr->stack_frame_index > 0) \
 339                 avr->stack_frame_index--;
 340 #else
 341 #define STACK_FRAME_PUSH()
 342 #define STACK_FRAME_POP()
 343 #endif
 344 #else /* CONFIG_SIMAVR_TRACE */
 345
 346 #define TRACE_JUMP()
 347 #define STACK_FRAME_PUSH()
 348 #define STACK_FRAME_POP()
 349
 350 #endif
 351
 352 /****************************************************************************\
 353  *
 354  * Helper functions for calculating the status register bit values.
 355  * See the Atmel data sheet for the instruction set for more info.
 356  *
 357 \****************************************************************************/
 358
 359 static uint8_t
 360 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 361 {
 362     uint8_t resb = res >> b & 0x1;
 363     uint8_t rdb = rd >> b & 0x1;
 364     uint8_t rrb = rr >> b & 0x1;
 365     return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
 366 }
 367
 368 static  uint8_t
 369 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 370 {
 371     uint8_t res7 = res >> 7 & 0x1;
 372     uint8_t rd7 = rd >> 7 & 0x1;
 373     uint8_t rr7 = rr >> 7 & 0x1;
 374     return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
 375 }
 376
 377 static  uint8_t
 378 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 379 {
 380     uint8_t resb = res >> b & 0x1;
 381     uint8_t rdb = rd >> b & 0x1;
 382     uint8_t rrb = rr >> b & 0x1;
 383     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 384 }
 385
 386 static  uint8_t
 387 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 388 {
 389     uint8_t res7 = res >> 7 & 0x1;
 390     uint8_t rd7 = rd >> 7 & 0x1;
 391     uint8_t rr7 = rr >> 7 & 0x1;
 392     return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
 393 }
 394
 395 static  uint8_t
 396 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
 397 {
 398     uint8_t resb = (res >> b) & 0x1;
 399     uint8_t rdb = (rd >> b) & 0x1;
 400     uint8_t rrb = (rr >> b) & 0x1;
 401     return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
 402 }
 403
 404 static  uint8_t
 405 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
 406 {
 407     res >>= 7; rd >>= 7; rr >>= 7;
 408     /* The atmel data sheet says the second term is ~rd7 for CP
 409      * but that doesn't make any sense. You be the judge. */
 410     return (rd & ~rr & ~res) | (~rd & rr & res);
 411 }
 412
 413 static inline int _avr_is_instruction_32_bits(avr_t * avr, uint32_t pc)
 414 {
 415         uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
 416         return  o == 0x9200 || // STS ! Store Direct to Data Space
 417                         o == 0x9000 || // LDS Load Direct from Data Space
 418                         o == 0x940c || // JMP Long Jump
 419                         o == 0x940d || // JMP Long Jump
 420                         o == 0x940e ||  // CALL Long Call to sub
 421                         o == 0x940f; // CALL Long Call to sub
 422 }
 423
 424 /*
 425  * Main opcode decoder
 426  *
 427  * The decoder was written by following the datasheet in no particular order.
 428  * As I went along, I noticed "bit patterns" that could be used to factor opcodes
 429  * However, a lot of these only became apparent later on, so SOME instructions
 430  * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
 431  * ones scream to be factored).
 432  * I assume that the decoder could easily be 2/3 of it's current size.
 433  *
 434  * + It lacks the "extended" XMega jumps.
 435  * + It also doesn't check whether the core it's
 436  *   emulating is supposed to have the fancy instructions, like multiply and such.
 437  *
 438  * for now all instructions take "one" cycle, the cycle+=<extra> needs to be added.
 439  */
 440 uint16_t avr_run_one(avr_t * avr)
 441 {
 442 #if CONFIG_SIMAVR_TRACE
 443         /*
 444          * this traces spurious reset or bad jumps
 445          */
 446         if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
 447                 avr->trace = 1;
 448                 STATE("RESET\n");
 449                 CRASH();
 450         }
 451         avr->touched[0] = avr->touched[1] = avr->touched[2] = 0;
 452 #endif
 453
 454         uint32_t        opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
 455         uint32_t        new_pc = avr->pc + 2;   // future "default" pc
 456         int             cycle = 1;
 457
 458         switch (opcode & 0xf000) {
 459                 case 0x0000: {
 460                         switch (opcode) {
 461                                 case 0x0000: {  // NOP
 462                                         STATE("nop\n");
 463                                 }       break;
 464                                 default: {
 465                                         switch (opcode & 0xfc00) {
 466                                                 case 0x0400: {  // CPC compare with carry 0000 01rd dddd rrrr
 467                                                         get_r_d_10(opcode);
 468                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 469                                                         STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 470                                                         if (res)
 471                                                                 avr->sreg[S_Z] = 0;
 472                                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 473                                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 474                                                         avr->sreg[S_N] = (res >> 7) & 1;
 475                                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 476                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 477                                                         SREG();
 478                                                 }       break;
 479                                                 case 0x0c00: {  // ADD without carry 0000 11 rd dddd rrrr
 480                                                         get_r_d_10(opcode);
 481                                                         uint8_t res = vd + vr;
 482                                                         if (r == d) {
 483                                                                 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
 484                                                         } else {
 485                                                                 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 486                                                         }
 487                                                         _avr_set_r(avr, d, res);
 488                                                         avr->sreg[S_Z] = res == 0;
 489                                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 490                                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 491                                                         avr->sreg[S_N] = (res >> 7) & 1;
 492                                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 493                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 494                                                         SREG();
 495                                                 }       break;
 496                                                 case 0x0800: {  // SBC substract with carry 0000 10rd dddd rrrr
 497                                                         get_r_d_10(opcode);
 498                                                         uint8_t res = vd - vr - avr->sreg[S_C];
 499                                                         STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 500                                                         _avr_set_r(avr, d, res);
 501                                                         if (res)
 502                                                                 avr->sreg[S_Z] = 0;
 503                                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 504                                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 505                                                         avr->sreg[S_N] = (res >> 7) & 1;
 506                                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 507                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 508                                                         SREG();
 509                                                 }       break;
 510                                                 default:
 511                                                         switch (opcode & 0xff00) {
 512                                                                 case 0x0100: {  // MOVW – Copy Register Word 0000 0001 dddd rrrr
 513                                                                         uint8_t d = ((opcode >> 4) & 0xf) << 1;
 514                                                                         uint8_t r = ((opcode) & 0xf) << 1;
 515                                                                         STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
 516                                                                         _avr_set_r(avr, d, avr->data[r]);
 517                                                                         _avr_set_r(avr, d+1, avr->data[r+1]);
 518                                                                 }       break;
 519                                                                 case 0x0200: {  // MULS – Multiply Signed 0000 0010 dddd rrrr
 520                                                                         int8_t r = 16 + (opcode & 0xf);
 521                                                                         int8_t d = 16 + ((opcode >> 4) & 0xf);
 522                                                                         int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 523                                                                         STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 524                                                                         _avr_set_r(avr, 0, res);
 525                                                                         _avr_set_r(avr, 1, res >> 8);
 526                                                                         avr->sreg[S_C] = (res >> 15) & 1;
 527                                                                         avr->sreg[S_Z] = res == 0;
 528                                                                         SREG();
 529                                                                 }       break;
 530                                                                 case 0x0300: {  // multiplications
 531                                                                         int8_t r = 16 + (opcode & 0x7);
 532                                                                         int8_t d = 16 + ((opcode >> 4) & 0x7);
 533                                                                         int16_t res = 0;
 534                                                                         uint8_t c = 0;
 535                                                                         const char * name = "";
 536                                                                         switch (opcode & 0x88) {
 537                                                                                 case 0x00:      // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
 538                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 539                                                                                         c = (res >> 15) & 1;
 540                                                                                         name = "mulsu";
 541                                                                                         break;
 542                                                                                 case 0x08:      // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
 543                                                                                         res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
 544                                                                                         c = (res >> 15) & 1;
 545                                                                                         res <<= 1;
 546                                                                                         name = "fmul";
 547                                                                                         break;
 548                                                                                 case 0x80:      // FMULS – Multiply Signed  0000 0011 1ddd 0rrr
 549                                                                                         res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 550                                                                                         c = (res >> 15) & 1;
 551                                                                                         res <<= 1;
 552                                                                                         name = "fmuls";
 553                                                                                         break;
 554                                                                                 case 0x88:      // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 0rrr
 555                                                                                         res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
 556                                                                                         c = (res >> 15) & 1;
 557                                                                                         res <<= 1;
 558                                                                                         name = "fmulsu";
 559                                                                                         break;
 560                                                                         }
 561                                                                         cycle++;
 562                                                                         STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
 563                                                                         _avr_set_r(avr, 0, res);
 564                                                                         _avr_set_r(avr, 1, res >> 8);
 565                                                                         avr->sreg[S_C] = c;
 566                                                                         avr->sreg[S_Z] = res == 0;
 567                                                                         SREG();
 568                                                                 }       break;
 569                                                                 default: _avr_invalid_opcode(avr);
 570                                                         }
 571                                         }
 572                                 }
 573                         }
 574                 }       break;
 575
 576                 case 0x1000: {
 577                         switch (opcode & 0xfc00) {
 578                                 case 0x1800: {  // SUB without carry 0000 10 rd dddd rrrr
 579                                         get_r_d_10(opcode);
 580                                         uint8_t res = vd - vr;
 581                                         STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 582                                         _avr_set_r(avr, d, res);
 583                                         avr->sreg[S_Z] = res == 0;
 584                                         avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
 585                                         avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
 586                                         avr->sreg[S_N] = (res >> 7) & 1;
 587                                         avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
 588                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 589                                         SREG();
 590                                 }       break;
 591                                 case 0x1000: {  // CPSE Compare, skip if equal 0000 10 rd dddd rrrr
 592                                         get_r_d_10(opcode);
 593                                         uint16_t res = vd == vr;
 594                                         STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":"not ");
 595                                         if (res) {
 596                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
 597                                                         new_pc += 4; cycle += 2;
 598                                                 } else {
 599                                                         new_pc += 2; cycle++;
 600                                                 }
 601                                         }
 602                                 }       break;
 603                                 case 0x1400: {  // CP Compare 0000 10 rd dddd rrrr
 604                                         get_r_d_10(opcode);
 605                                         uint8_t res = vd - vr;
 606                                         STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 607                                         avr->sreg[S_Z] = res == 0;
 608                                         avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
 609                                         avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
 610                                         avr->sreg[S_N] = res >> 7;
 611                                         avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
 612                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 613                                         SREG();
 614                                 }       break;
 615                                 case 0x1c00: {  // ADD with carry 0001 11 rd dddd rrrr
 616                                         get_r_d_10(opcode);
 617                                         uint8_t res = vd + vr + avr->sreg[S_C];
 618                                         if (r == d) {
 619                                                 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
 620                                         } else {
 621                                                 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
 622                                         }
 623                                         _avr_set_r(avr, d, res);
 624                                         avr->sreg[S_Z] = res == 0;
 625                                         avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
 626                                         avr->sreg[S_V] = get_add_overflow(res, vd, vr);
 627                                         avr->sreg[S_N] = (res >> 7) & 1;
 628                                         avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
 629                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 630                                         SREG();
 631                                 }       break;
 632                                 default: _avr_invalid_opcode(avr);
 633                         }
 634                 }       break;
 635
 636                 case 0x2000: {
 637                         switch (opcode & 0xfc00) {
 638                                 case 0x2000: {  // AND  0010 00rd dddd rrrr
 639                                         get_r_d_10(opcode);
 640                                         uint8_t res = vd & vr;
 641                                         if (r == d) {
 642                                                 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
 643                                         } else {
 644                                                 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 645                                         }
 646                                         _avr_set_r(avr, d, res);
 647                                         avr->sreg[S_Z] = res == 0;
 648                                         avr->sreg[S_N] = (res >> 7) & 1;
 649                                         avr->sreg[S_V] = 0;
 650                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 651                                         SREG();
 652                                 }       break;
 653                                 case 0x2400: {  // EOR  0010 01rd dddd rrrr
 654                                         get_r_d_10(opcode);
 655                                         uint8_t res = vd ^ vr;
 656                                         if (r==d) {
 657                                                 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
 658                                         } else {
 659                                                 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 660                                         }
 661                                         _avr_set_r(avr, d, res);
 662                                         avr->sreg[S_Z] = res == 0;
 663                                         avr->sreg[S_N] = (res >> 7) & 1;
 664                                         avr->sreg[S_V] = 0;
 665                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 666                                         SREG();
 667                                 }       break;
 668                                 case 0x2800: {  // OR Logical OR        0010 10rd dddd rrrr
 669                                         get_r_d_10(opcode);
 670                                         uint8_t res = vd | vr;
 671                                         STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 672                                         _avr_set_r(avr, d, res);
 673                                         avr->sreg[S_Z] = res == 0;
 674                                         avr->sreg[S_N] = (res >> 7) & 1;
 675                                         avr->sreg[S_V] = 0;
 676                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 677                                         SREG();
 678                                 }       break;
 679                                 case 0x2c00: {  // MOV  0010 11rd dddd rrrr
 680                                         get_r_d_10(opcode);
 681                                         uint8_t res = vr;
 682                                         STATE("mov %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
 683                                         _avr_set_r(avr, d, res);
 684                                 }       break;
 685                                 default: _avr_invalid_opcode(avr);
 686                         }
 687                 }       break;
 688
 689                 case 0x3000: {  // CPI 0011 KKKK rrrr KKKK
 690                         get_k_r16(opcode);
 691                         uint8_t vr = avr->data[r];
 692                         uint8_t res = vr - k;
 693                         STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
 694
 695                         avr->sreg[S_Z] = res == 0;
 696                         avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
 697                         avr->sreg[S_V] = get_compare_overflow(res, vr, k);
 698                         avr->sreg[S_N] = (res >> 7) & 1;
 699                         avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
 700                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 701                         SREG();
 702                 }       break;
 703
 704                 case 0x4000: {  // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
 705                         get_k_r16(opcode);
 706                         uint8_t vr = avr->data[r];
 707                         uint8_t res = vr - k - avr->sreg[S_C];
 708                         STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 709                         _avr_set_r(avr, r, res);
 710                         if (res)
 711                                 avr->sreg[S_Z] = 0;
 712                         avr->sreg[S_N] = (res >> 7) & 1;
 713                         avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
 714                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 715                         SREG();
 716                 }       break;
 717
 718                 case 0x5000: {  // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
 719                         get_k_r16(opcode);
 720                         uint8_t vr = avr->data[r];
 721                         uint8_t res = vr - k;
 722                         STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
 723                         _avr_set_r(avr, r, res);
 724                         avr->sreg[S_Z] = res  == 0;
 725                         avr->sreg[S_N] = (res >> 7) & 1;
 726                         avr->sreg[S_C] = k > vr;
 727                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 728                         SREG();
 729                 }       break;
 730
 731                 case 0x6000: {  // ORI aka SBR  Logical AND with Immediate      0110 kkkk dddd kkkk
 732                         get_k_r16(opcode);
 733                         uint8_t res = avr->data[r] | k;
 734                         STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 735                         _avr_set_r(avr, r, res);
 736                         avr->sreg[S_Z] = res == 0;
 737                         avr->sreg[S_N] = (res >> 7) & 1;
 738                         avr->sreg[S_V] = 0;
 739                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 740                         SREG();
 741                 }       break;
 742
 743                 case 0x7000: {  // ANDI Logical AND with Immediate      0111 kkkk dddd kkkk
 744                         get_k_r16(opcode);
 745                         uint8_t res = avr->data[r] & k;
 746                         STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
 747                         _avr_set_r(avr, r, res);
 748                         avr->sreg[S_Z] = res == 0;
 749                         avr->sreg[S_N] = (res >> 7) & 1;
 750                         avr->sreg[S_V] = 0;
 751                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
 752                         SREG();
 753                 }       break;
 754
 755                 case 0xa000:
 756                 case 0x8000: {
 757                         switch (opcode & 0xd008) {
 758                                 case 0xa000:
 759                                 case 0x8000: {  // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
 760                                         uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 761                                         uint8_t r = (opcode >> 4) & 0x1f;
 762                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 763
 764                                         if (opcode & 0x0200) {
 765                                                 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 766                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 767                                         } else {
 768                                                 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 769                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 770                                         }
 771                                         cycle += 2;
 772                                 }       break;
 773                                 case 0xa008:
 774                                 case 0x8008: {  // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
 775                                         uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
 776                                         uint8_t r = (opcode >> 4) & 0x1f;
 777                                         uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
 778
 779                                         if (opcode & 0x0200) {
 780                                                 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
 781                                                 _avr_set_ram(avr, v+q, avr->data[r]);
 782                                         } else {
 783                                                 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
 784                                                 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
 785                                         }
 786                                         cycle += 2;
 787                                 }       break;
 788                                 default: _avr_invalid_opcode(avr);
 789                         }
 790                 }       break;
 791
 792                 case 0x9000: {
 793                         /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
 794                         if ((opcode & 0xff0f) == 0x9408) {
 795                                 uint8_t b = (opcode >> 4) & 7;
 796                                 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
 797                                 avr->sreg[b] = (opcode & 0x0080) == 0;
 798                                 SREG();
 799                         } else switch (opcode) {
 800                                 case 0x9588: { // SLEEP
 801                                         STATE("sleep\n");
 802                                         avr->state = cpu_Sleeping;
 803                                 }       break;
 804                                 case 0x9598: { // BREAK
 805                                         STATE("break\n");
 806                                         if (avr->gdb) {
 807                                                 // if gdb is on, we break here as in here
 808                                                 // and we do so until gdb restores the instruction
 809                                                 // that was here before
 810                                                 avr->state = cpu_StepDone;
 811                                                 new_pc = avr->pc;
 812                                                 cycle = 0;
 813                                         }
 814                                 }       break;
 815                                 case 0x95a8: { // WDR
 816                                         STATE("wdr\n");
 817                                         avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);
 818                                 }       break;
 819                                 case 0x95e8: { // SPM
 820                                         STATE("spm\n");
 821                                         avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
 822                                 }       break;
 823                                 case 0x9409:   // IJMP Indirect jump                                    1001 0100 0000 1001
 824                                 case 0x9419:   // EIJMP Indirect jump                                   1001 0100 0001 1001   bit 4 is "indirect"
 825                                 case 0x9509:   // ICALL Indirect Call to Subroutine             1001 0101 0000 1001
 826                                 case 0x9519: { // EICALL Indirect Call to Subroutine    1001 0101 0001 1001   bit 8 is "push pc"
 827                                         int e = opcode & 0x10;
 828                                         int p = opcode & 0x100;
 829                                         if (e && !avr->eind)
 830                                                 _avr_invalid_opcode(avr);
 831                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 832                                         if (e)
 833                                                 z |= avr->data[avr->eind] << 16;
 834                                         STATE("%si%s Z[%04x]\n", e?"e":"", p?"call":"jmp", z << 1);
 835                                         if (p) {
 836                                                 cycle++;
 837                                                 _avr_push16(avr, new_pc >> 1);
 838                                         }
 839                                         new_pc = z << 1;
 840                                         cycle++;
 841                                         TRACE_JUMP();
 842                                 }       break;
 843                                 case 0x9518:    // RETI
 844                                 case 0x9508: {  // RET
 845                                         new_pc = _avr_pop16(avr) << 1;
 846                                         if (opcode & 0x10)      // reti
 847                                                 avr->sreg[S_I] = 1;
 848                                         cycle += 3;
 849                                         STATE("ret%s\n", opcode & 0x10 ? "i" : "");
 850                                         TRACE_JUMP();
 851                                         STACK_FRAME_POP();
 852                                 }       break;
 853                                 case 0x95c8: {  // LPM Load Program Memory R0 <- (Z)
 854                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 855                                         STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
 856                                         _avr_set_r(avr, 0, avr->flash[z]);
 857                                 }       break;
 858                                 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
 859                                 case 0x9478:
 860                                 {       // BSET 1001 0100 0ddd 1000
 861                                         uint8_t b = (opcode >> 4) & 7;
 862                                         avr->sreg[b] = 1;
 863                                         STATE("bset %c\n", _sreg_bit_name[b]);
 864                                         SREG();
 865                                 }       break;
 866                                 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
 867                                 case 0x94f8:
 868                                 {       // BSET 1001 0100 0ddd 1000
 869                                         uint8_t b = (opcode >> 4) & 7;
 870                                         avr->sreg[b] = 0;
 871                                         STATE("bclr %c\n", _sreg_bit_name[b]);
 872                                         SREG();
 873                                 }       break;
 874                                 default:  {
 875                                         switch (opcode & 0xfe0f) {
 876                                                 case 0x9000: {  // LDS Load Direct from Data Space, 32 bits
 877                                                         uint8_t r = (opcode >> 4) & 0x1f;
 878                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 879                                                         new_pc += 2;
 880                                                         STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
 881                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 882                                                         cycle++;
 883                                                 }       break;
 884                                                 case 0x9005:
 885                                                 case 0x9004: {  // LPM Load Program Memory 1001 000d dddd 01oo
 886                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
 887                                                         uint8_t r = (opcode >> 4) & 0x1f;
 888                                                         int op = opcode & 3;
 889                                                         STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
 890                                                         _avr_set_r(avr, r, avr->flash[z]);
 891                                                         if (op == 1) {
 892                                                                 z++;
 893                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 894                                                                 _avr_set_r(avr, R_ZL, z);
 895                                                         }
 896                                                         cycle += 2;
 897                                                 }       break;
 898                                                 case 0x9006:
 899                                                 case 0x9007: {  // ELPM Extended Load Program Memory 1001 000d dddd 01oo
 900                                                         if (!avr->rampz)
 901                                                                 _avr_invalid_opcode(avr);
 902                                                         uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
 903                                                         uint8_t r = (opcode >> 4) & 0x1f;
 904                                                         int op = opcode & 3;
 905                                                         STATE("elpm %s, (Z[%02x:%04x]%s)\n", avr_regname(r), z >> 16, z&0xffff, opcode?"+":"");
 906                                                         _avr_set_r(avr, r, avr->flash[z]);
 907                                                         if (op == 3) {
 908                                                                 z++;
 909                                                                 _avr_set_r(avr, avr->rampz, z >> 16);
 910                                                                 _avr_set_r(avr, R_ZH, z >> 8);
 911                                                                 _avr_set_r(avr, R_ZL, z);
 912                                                         }
 913                                                         cycle += 2;
 914                                                 }       break;
 915                                                 case 0x900c:
 916                                                 case 0x900d:
 917                                                 case 0x900e: {  // LD Load Indirect from Data using X 1001 000r rrrr 11oo
 918                                                         int op = opcode & 3;
 919                                                         uint8_t r = (opcode >> 4) & 0x1f;
 920                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 921                                                         STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
 922
 923                                                         if (op == 2) x--;
 924                                                         _avr_set_r(avr, r, _avr_get_ram(avr, x));
 925                                                         if (op == 1) x++;
 926                                                         _avr_set_r(avr, R_XH, x >> 8);
 927                                                         _avr_set_r(avr, R_XL, x);
 928                                                 }       break;
 929                                                 case 0x920c:
 930                                                 case 0x920d:
 931                                                 case 0x920e: {  // ST Store Indirect Data Space X 1001 001r rrrr 11oo
 932                                                         int op = opcode & 3;
 933                                                         uint8_t r = (opcode >> 4) & 0x1f;
 934                                                         uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
 935                                                         STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 936                                                         cycle++;
 937                                                         if (op == 2) x--;
 938                                                         _avr_set_ram(avr, x, avr->data[r]);
 939                                                         if (op == 1) x++;
 940                                                         _avr_set_r(avr, R_XH, x >> 8);
 941                                                         _avr_set_r(avr, R_XL, x);
 942                                                 }       break;
 943                                                 case 0x9009:
 944                                                 case 0x900a: {  // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
 945                                                         int op = opcode & 3;
 946                                                         uint8_t r = (opcode >> 4) & 0x1f;
 947                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 948                                                         STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
 949                                                         cycle++;
 950                                                         if (op == 2) y--;
 951                                                         _avr_set_r(avr, r, _avr_get_ram(avr, y));
 952                                                         if (op == 1) y++;
 953                                                         _avr_set_r(avr, R_YH, y >> 8);
 954                                                         _avr_set_r(avr, R_YL, y);
 955                                                 }       break;
 956                                                 case 0x9209:
 957                                                 case 0x920a: {  // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
 958                                                         int op = opcode & 3;
 959                                                         uint8_t r = (opcode >> 4) & 0x1f;
 960                                                         uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
 961                                                         STATE("st %sY[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 962                                                         cycle++;
 963                                                         if (op == 2) y--;
 964                                                         _avr_set_ram(avr, y, avr->data[r]);
 965                                                         if (op == 1) y++;
 966                                                         _avr_set_r(avr, R_YH, y >> 8);
 967                                                         _avr_set_r(avr, R_YL, y);
 968                                                 }       break;
 969                                                 case 0x9200: {  // STS ! Store Direct to Data Space, 32 bits
 970                                                         uint8_t r = (opcode >> 4) & 0x1f;
 971                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
 972                                                         new_pc += 2;
 973                                                         STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
 974                                                         _avr_set_ram(avr, x, avr->data[r]);
 975                                                 }       break;
 976                                                 case 0x9001:
 977                                                 case 0x9002: {  // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
 978                                                         int op = opcode & 3;
 979                                                         uint8_t r = (opcode >> 4) & 0x1f;
 980                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
 981                                                         STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
 982                                                         if (op == 2) z--;
 983                                                         _avr_set_r(avr, r, _avr_get_ram(avr, z));
 984                                                         if (op == 1) z++;
 985                                                         _avr_set_r(avr, R_ZH, z >> 8);
 986                                                         _avr_set_r(avr, R_ZL, z);
 987                                                 }       break;
 988                                                 case 0x9201:
 989                                                 case 0x9202: {  // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
 990                                                         int op = opcode & 3;
 991                                                         uint8_t r = (opcode >> 4) & 0x1f;
 992                                                         uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
 993                                                         STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
 994                                                         if (op == 2) z--;
 995                                                         _avr_set_ram(avr, z, avr->data[r]);
 996                                                         if (op == 1) z++;
 997                                                         _avr_set_r(avr, R_ZH, z >> 8);
 998                                                         _avr_set_r(avr, R_ZL, z);
 999                                                 }       break;
1000                                                 case 0x900f: {  // POP 1001 000d dddd 1111
1001                                                         uint8_t r = (opcode >> 4) & 0x1f;
1002                                                         _avr_set_r(avr, r, _avr_pop8(avr));
1003                                                         uint16_t sp = _avr_sp_get(avr);
1004                                                         STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
1005                                                         cycle++;
1006                                                 }       break;
1007                                                 case 0x920f: {  // PUSH 1001 001d dddd 1111
1008                                                         uint8_t r = (opcode >> 4) & 0x1f;
1009                                                         _avr_push8(avr, avr->data[r]);
1010                                                         uint16_t sp = _avr_sp_get(avr);
1011                                                         STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
1012                                                         cycle++;
1013                                                 }       break;
1014                                                 case 0x9400: {  // COM – One’s Complement
1015                                                         uint8_t r = (opcode >> 4) & 0x1f;
1016                                                         uint8_t res = 0xff - avr->data[r];
1017                                                         STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1018                                                         _avr_set_r(avr, r, res);
1019                                                         avr->sreg[S_Z] = res == 0;
1020                                                         avr->sreg[S_N] = res >> 7;
1021                                                         avr->sreg[S_V] = 0;
1022                                                         avr->sreg[S_C] = 1;
1023                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1024                                                         SREG();
1025                                                 }       break;
1026                                                 case 0x9401: {  // NEG – One’s Complement
1027                                                         uint8_t r = (opcode >> 4) & 0x1f;
1028                                                         uint8_t rd = avr->data[r];
1029                                                         uint8_t res = 0x00 - rd;
1030                                                         STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
1031                                                         _avr_set_r(avr, r, res);
1032                                                         avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
1033                                                         avr->sreg[S_Z] = res == 0;
1034                                                         avr->sreg[S_N] = res >> 7;
1035                                                         avr->sreg[S_V] = res == 0x80;
1036                                                         avr->sreg[S_C] = res != 0;
1037                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1038                                                         SREG();
1039                                                 }       break;
1040                                                 case 0x9402: {  // SWAP – Swap Nibbles
1041                                                         uint8_t r = (opcode >> 4) & 0x1f;
1042                                                         uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1043                                                         STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1044                                                         _avr_set_r(avr, r, res);
1045                                                 }       break;
1046                                                 case 0x9403: {  // INC – Increment
1047                                                         uint8_t r = (opcode >> 4) & 0x1f;
1048                                                         uint8_t res = avr->data[r] + 1;
1049                                                         STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1050                                                         _avr_set_r(avr, r, res);
1051                                                         avr->sreg[S_Z] = res == 0;
1052                                                         avr->sreg[S_N] = res >> 7;
1053                                                         avr->sreg[S_V] = res == 0x7f;
1054                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1055                                                         SREG();
1056                                                 }       break;
1057                                                 case 0x9405: {  // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1058                                                         uint8_t r = (opcode >> 4) & 0x1f;
1059                                                         uint8_t vr = avr->data[r];
1060                                                         uint8_t res = (vr >> 1) | (vr & 0x80);
1061                                                         STATE("asr %s[%02x]\n", avr_regname(r), vr);
1062                                                         _avr_set_r(avr, r, res);
1063                                                         avr->sreg[S_Z] = res == 0;
1064                                                         avr->sreg[S_C] = vr & 1;
1065                                                         avr->sreg[S_N] = res >> 7;
1066                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1067                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1068                                                         SREG();
1069                                                 }       break;
1070                                                 case 0x9406: {  // LSR 1001 010d dddd 0110
1071                                                         uint8_t r = (opcode >> 4) & 0x1f;
1072                                                         uint8_t vr = avr->data[r];
1073                                                         uint8_t res = vr >> 1;
1074                                                         STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1075                                                         _avr_set_r(avr, r, res);
1076                                                         avr->sreg[S_Z] = res == 0;
1077                                                         avr->sreg[S_C] = vr & 1;
1078                                                         avr->sreg[S_N] = 0;
1079                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1080                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1081                                                         SREG();
1082                                                 }       break;
1083                                                 case 0x9407: {  // ROR 1001 010d dddd 0111
1084                                                         uint8_t r = (opcode >> 4) & 0x1f;
1085                                                         uint8_t vr = avr->data[r];
1086                                                         uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1087                                                         STATE("ror %s[%02x]\n", avr_regname(r), vr);
1088                                                         _avr_set_r(avr, r, res);
1089                                                         avr->sreg[S_Z] = res == 0;
1090                                                         avr->sreg[S_C] = vr & 1;
1091                                                         avr->sreg[S_N] = 0;
1092                                                         avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1093                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1094                                                         SREG();
1095                                                 }       break;
1096                                                 case 0x940a: {  // DEC – Decrement
1097                                                         uint8_t r = (opcode >> 4) & 0x1f;
1098                                                         uint8_t res = avr->data[r] - 1;
1099                                                         STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1100                                                         _avr_set_r(avr, r, res);
1101                                                         avr->sreg[S_Z] = res == 0;
1102                                                         avr->sreg[S_N] = res >> 7;
1103                                                         avr->sreg[S_V] = res == 0x80;
1104                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1105                                                         SREG();
1106                                                 }       break;
1107                                                 case 0x940c:
1108                                                 case 0x940d: {  // JMP Long Call to sub, 32 bits
1109                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1110                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1111                                                         a = (a << 16) | x;
1112                                                         STATE("jmp 0x%06x\n", a);
1113                                                         new_pc = a << 1;
1114                                                         cycle += 2;
1115                                                         TRACE_JUMP();
1116                                                 }       break;
1117                                                 case 0x940e:
1118                                                 case 0x940f: {  // CALL Long Call to sub, 32 bits
1119                                                         uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1120                                                         uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1121                                                         a = (a << 16) | x;
1122                                                         STATE("call 0x%06x\n", a);
1123                                                         new_pc += 2;
1124                                                         _avr_push16(avr, new_pc >> 1);
1125                                                         new_pc = a << 1;
1126                                                         cycle += 3;     // 4 cycles
1127                                                         TRACE_JUMP();
1128                                                         STACK_FRAME_PUSH();
1129                                                 }       break;
1130
1131                                                 default: {
1132                                                         switch (opcode & 0xff00) {
1133                                                                 case 0x9600: {  // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1134                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1135                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1136                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1137                                                                         uint32_t res = rdl | (rdh << 8);
1138                                                                         STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1139                                                                         res += k;
1140                                                                         _avr_set_r(avr, r + 1, res >> 8);
1141                                                                         _avr_set_r(avr, r, res);
1142                                                                         avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1143                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1144                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1145                                                                         avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1146                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1147                                                                         SREG();
1148                                                                         cycle++;
1149                                                                 }       break;
1150                                                                 case 0x9700: {  // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1151                                                                         uint8_t r = 24 + ((opcode >> 3) & 0x6);
1152                                                                         uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1153                                                                         uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1154                                                                         uint32_t res = rdl | (rdh << 8);
1155                                                                         STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1156                                                                         res -= k;
1157                                                                         _avr_set_r(avr, r + 1, res >> 8);
1158                                                                         _avr_set_r(avr, r, res);
1159                                                                         avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1160                                                                         avr->sreg[S_Z] = (res & 0xffff) == 0;
1161                                                                         avr->sreg[S_N] = (res >> 15) & 1;
1162                                                                         avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1163                                                                         avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1164                                                                         SREG();
1165                                                                         cycle++;
1166                                                                 }       break;
1167                                                                 case 0x9800: {  // CBI - Clear Bit in I/O Registe 1001 1000 AAAA Abbb
1168                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1169                                                                         uint8_t b = opcode & 0x7;
1170                                                                         uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1171                                                                         STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1172                                                                         _avr_set_ram(avr, io, res);
1173                                                                         cycle++;
1174                                                                 }       break;
1175                                                                 case 0x9900: {  // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1176                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1177                                                                         uint8_t b = opcode & 0x7;
1178                                                                         uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1179                                                                         STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":"not ");
1180                                                                         if (!res) {
1181                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1182                                                                                         new_pc += 4; cycle += 2;
1183                                                                                 } else {
1184                                                                                         new_pc += 2; cycle++;
1185                                                                                 }
1186                                                                         }
1187                                                                 }       break;
1188                                                                 case 0x9a00: {  // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1189                                                                         uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1190                                                                         uint8_t b = opcode & 0x7;
1191                                                                         uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1192                                                                         STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1193                                                                         _avr_set_ram(avr, io, res);
1194                                                                         cycle++;
1195                                                                 }       break;
1196                                                                 case 0x9b00: {  // SBIS - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1197                                                                         uint8_t io = (opcode >> 3) & 0x1f;
1198                                                                         uint8_t b = opcode & 0x7;
1199                                                                         uint8_t res = _avr_get_ram(avr, io + 32) & (1 << b);
1200                                                                         STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":"not ");
1201                                                                         if (res) {
1202                                                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1203                                                                                         new_pc += 4; cycle += 2;
1204                                                                                 } else {
1205                                                                                         new_pc += 2; cycle++;
1206                                                                                 }
1207                                                                         }
1208                                                                 }       break;
1209                                                                 default:
1210                                                                         switch (opcode & 0xfc00) {
1211                                                                                 case 0x9c00: {  // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1212                                                                                         get_r_d_10(opcode);
1213                                                                                         uint16_t res = vd * vr;
1214                                                                                         STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1215                                                                                         _avr_set_r(avr, 0, res);
1216                                                                                         _avr_set_r(avr, 1, res >> 8);
1217                                                                                         avr->sreg[S_Z] = res == 0;
1218                                                                                         avr->sreg[S_C] = (res >> 15) & 1;
1219                                                                                         SREG();
1220                                                                                 }       break;
1221                                                                                 default: _avr_invalid_opcode(avr);
1222                                                                         }
1223                                                         }
1224                                                 }       break;
1225                                         }
1226                                 }       break;
1227                         }
1228                 }       break;
1229
1230                 case 0xb000: {
1231                         switch (opcode & 0xf800) {
1232                                 case 0xb800: {  // OUT A,Rr 1011 1AAr rrrr AAAA
1233                                         uint8_t r = (opcode >> 4) & 0x1f;
1234                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1235                                         STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1236                                         _avr_set_ram(avr, A, avr->data[r]);
1237                                 }       break;
1238                                 case 0xb000: {  // IN Rd,A 1011 0AAr rrrr AAAA
1239                                         uint8_t r = (opcode >> 4) & 0x1f;
1240                                         uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1241                                         STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1242                                         _avr_set_r(avr, r, _avr_get_ram(avr, A));
1243                                 }       break;
1244                                 default: _avr_invalid_opcode(avr);
1245                         }
1246                 }       break;
1247
1248                 case 0xc000: {
1249                         // RJMP 1100 kkkk kkkk kkkk
1250                         short o = ((short)(opcode << 4)) >> 4;
1251                         STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1252                         new_pc = new_pc + (o << 1);
1253                         cycle++;
1254                         TRACE_JUMP();
1255                 }       break;
1256
1257                 case 0xd000: {
1258                         // RCALL 1100 kkkk kkkk kkkk
1259                         short o = ((short)(opcode << 4)) >> 4;
1260                         STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1261                         _avr_push16(avr, new_pc >> 1);
1262                         new_pc = new_pc + (o << 1);
1263                         cycle += 2;
1264                         // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1265                         if (o != 0) {
1266                                 TRACE_JUMP();
1267                                 STACK_FRAME_PUSH();
1268                         }
1269                 }       break;
1270
1271                 case 0xe000: {  // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1272                         uint8_t d = 16 + ((opcode >> 4) & 0xf);
1273                         uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1274                         STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1275                         _avr_set_r(avr, d, k);
1276                 }       break;
1277
1278                 case 0xf000: {
1279                         switch (opcode & 0xfe00) {
1280                                 case 0xf000:
1281                                 case 0xf200:
1282                                 case 0xf400:
1283                                 case 0xf600: {  // All the SREG branches
1284                                         short o = ((short)(opcode << 6)) >> 9; // offset
1285                                         uint8_t s = opcode & 7;
1286                                         int set = (opcode & 0x0400) == 0;               // this bit means BRXC otherwise BRXS
1287                                         int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1288                                         const char *names[2][8] = {
1289                                                         { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1290                                                         { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1291                                         };
1292                                         if (names[set][s]) {
1293                                                 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1294                                         } else {
1295                                                 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1296                                         }
1297                                         if (branch) {
1298                                                 cycle++;
1299                                                 new_pc = new_pc + (o << 1);
1300                                         }
1301                                 }       break;
1302                                 case 0xf800:
1303                                 case 0xf900: {  // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1304                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1305                                         uint8_t s = opcode & 7;
1306                                         uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1307                                         STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1308                                         _avr_set_r(avr, r, v);
1309                                 }       break;
1310                                 case 0xfa00:
1311                                 case 0xfb00:{   // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1312                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1313                                         uint8_t s = opcode & 7;
1314                                         STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1315                                         avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1316                                         SREG();
1317                                 }       break;
1318                                 case 0xfc00:
1319                                 case 0xfe00: {  // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1320                                         uint8_t r = (opcode >> 4) & 0x1f; // register index
1321                                         uint8_t s = opcode & 7;
1322                                         int set = (opcode & 0x0200) != 0;
1323                                         int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1324                                         STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1325                                         if (branch) {
1326                                                 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1327                                                         new_pc += 4; cycle += 2;
1328                                                 } else {
1329                                                         new_pc += 2; cycle++;
1330                                                 }
1331                                         }
1332                                 }       break;
1333                                 default: _avr_invalid_opcode(avr);
1334                         }
1335                 }       break;
1336
1337                 default: _avr_invalid_opcode(avr);
1338
1339         }
1340         avr->cycle += cycle;
1341         return new_pc;
1342 }
1343
1344