4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
30 const char * _sreg_bit_name = "cznvshti";
33 * Handle "touching" registers, marking them changed.
34 * This is used only for debugging purposes to be able to
35 * print the effects of each instructions on registers
37 #if CONFIG_SIMAVR_TRACE
38 #define REG_TOUCH(a, r) (a)->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
39 #define REG_ISTOUCHED(a, r) ((a)->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
42 * This allows a "special case" to skip indtruction tracing when in these
43 * symbols. since printf() is useful to have, but generates a lot of cycles
45 int dont_trace(const char * name)
48 !strcmp(name, "uart_putchar") ||
49 !strcmp(name, "fputc") ||
50 !strcmp(name, "printf") ||
51 !strcmp(name, "vfprintf") ||
52 !strcmp(name, "__ultoa_invert") ||
53 !strcmp(name, "__prologue_saves__") ||
54 !strcmp(name, "__epilogue_restores__"));
59 #define STATE(_f, args...) { \
61 if (avr->codeline[avr->pc>>1]) {\
62 const char * symn = avr->codeline[avr->pc>>1]->symbol; \
63 int dont = 0 && dont_trace(symn);\
64 if (dont!=donttrace) { \
69 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
71 printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
74 #define SREG() if (avr->trace && donttrace == 0) {\
75 printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
76 for (int _sbi = 0; _sbi < 8; _sbi++)\
77 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
81 #define REG_TOUCH(a, r)
82 #define STATE(_f, args...)
87 * Set a register (r < 256)
88 * if it's an IO regisrer (> 31) also (try to) call any callback that was
89 * registered to track changes to that register.
91 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
98 for (int i = 0; i < 8; i++)
99 avr->sreg[i] = (avr->data[R_SREG] & (1 << i)) != 0;
103 uint8_t io = AVR_DATA_TO_IO(r);
105 avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
108 if (avr->io[io].irq) {
109 avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
110 for (int i = 0; i < 8; i++)
111 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
118 * Stack pointer access
120 inline uint16_t _avr_sp_get(avr_t * avr)
122 return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
125 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
127 _avr_set_r(avr, R_SPL, sp);
128 _avr_set_r(avr, R_SPH, sp >> 8);
132 * Set any address to a value; split between registers and SRAM
134 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
137 _avr_set_r(avr, addr, v);
139 avr_core_watch_write(avr, addr, v);
143 * Get a value from SRAM.
145 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
147 if (addr > 31 && addr < 256) {
148 uint8_t io = AVR_DATA_TO_IO(addr);
150 avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
152 if (avr->io[io].irq) {
153 uint8_t v = avr->data[addr];
154 avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
155 for (int i = 0; i < 8; i++)
156 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
159 return avr_core_watch_read(avr, addr);
163 * Stack push accessors. Push/pop 8 and 16 bits
165 static inline void _avr_push8(avr_t * avr, uint16_t v)
167 uint16_t sp = _avr_sp_get(avr);
168 _avr_set_ram(avr, sp, v);
169 _avr_sp_set(avr, sp-1);
172 static inline uint8_t _avr_pop8(avr_t * avr)
174 uint16_t sp = _avr_sp_get(avr) + 1;
175 uint8_t res = _avr_get_ram(avr, sp);
176 _avr_sp_set(avr, sp);
180 inline void _avr_push16(avr_t * avr, uint16_t v)
182 _avr_push8(avr, v >> 8);
186 static inline uint16_t _avr_pop16(avr_t * avr)
188 uint16_t res = _avr_pop8(avr);
189 res |= _avr_pop8(avr) << 8;
194 * "Pretty" register names
196 const char * reg_names[255] = {
197 [R_XH] = "XH", [R_XL] = "XL",
198 [R_YH] = "YH", [R_YL] = "YL",
199 [R_ZH] = "ZH", [R_ZL] = "ZL",
200 [R_SPH] = "SPH", [R_SPL] = "SPL",
205 const char * avr_regname(uint8_t reg)
207 if (!reg_names[reg]) {
210 sprintf(tt, "r%d", reg);
212 sprintf(tt, "io:%02x", reg);
213 reg_names[reg] = strdup(tt);
215 return reg_names[reg];
219 * Called when an invalid opcode is decoded
221 static void _avr_invalid_opcode(avr_t * avr)
223 #if CONFIG_SIMAVR_TRACE
224 printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n",
225 avr->pc, avr->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
227 printf("\e[31m*** %04x: Invalid Opcode SP=%04x O=%04x \e[0m\n",
228 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
232 #if CONFIG_SIMAVR_TRACE
234 * Dump changed registers when tracing
236 void avr_dump_state(avr_t * avr)
238 if (!avr->trace || donttrace)
243 for (int r = 0; r < 3 && !doit; r++)
249 const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
250 for (int i = 0; i < 4; i++)
251 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
252 REG_TOUCH(avr, r16[i]);
253 REG_TOUCH(avr, r16[i]+1);
256 for (int i = 0; i < 3*32; i++)
257 if (REG_ISTOUCHED(avr, i)) {
258 printf("%s=%02x ", avr_regname(i), avr->data[i]);
264 #define get_r_d_10(o) \
265 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
266 const uint8_t d = (o >> 4) & 0x1f;\
267 const uint8_t vd = avr->data[d], vr =avr->data[r];
268 #define get_k_r16(o) \
269 const uint8_t r = 16 + ((o >> 4) & 0xf); \
270 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
273 * Add a "jump" address to the jump trace buffer
275 #if CONFIG_SIMAVR_TRACE
276 #define TRACE_JUMP()\
277 avr->old[avr->old_pci].pc = avr->pc;\
278 avr->old[avr->old_pci].sp = _avr_sp_get(avr);\
279 avr->old_pci = (avr->old_pci + 1) & (OLD_PC_SIZE-1);\
282 #define STACK_FRAME_PUSH()\
283 avr->stack_frame[avr->stack_frame_index].pc = avr->pc;\
284 avr->stack_frame[avr->stack_frame_index].sp = _avr_sp_get(avr);\
285 avr->stack_frame_index++;
286 #define STACK_FRAME_POP()\
287 if (avr->stack_frame_index > 0) \
288 avr->stack_frame_index--;
290 #define STACK_FRAME_PUSH()
291 #define STACK_FRAME_POP()
293 #else /* CONFIG_SIMAVR_TRACE */
296 #define STACK_FRAME_PUSH()
297 #define STACK_FRAME_POP()
301 /****************************************************************************\
303 * Helper functions for calculating the status register bit values.
304 * See the Atmel data sheet for the instuction set for more info.
306 \****************************************************************************/
309 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
311 uint8_t resb = res >> b & 0x1;
312 uint8_t rdb = rd >> b & 0x1;
313 uint8_t rrb = rr >> b & 0x1;
314 return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
318 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
320 uint8_t res7 = res >> 7 & 0x1;
321 uint8_t rd7 = rd >> 7 & 0x1;
322 uint8_t rr7 = rr >> 7 & 0x1;
323 return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
327 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
329 uint8_t resb = res >> b & 0x1;
330 uint8_t rdb = rd >> b & 0x1;
331 uint8_t rrb = rr >> b & 0x1;
332 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
336 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
338 uint8_t res7 = res >> 7 & 0x1;
339 uint8_t rd7 = rd >> 7 & 0x1;
340 uint8_t rr7 = rr >> 7 & 0x1;
341 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
345 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
347 uint8_t resb = (res >> b) & 0x1;
348 uint8_t rdb = (rd >> b) & 0x1;
349 uint8_t rrb = (rr >> b) & 0x1;
350 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
354 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
356 res >>= 7; rd >>= 7; rr >>= 7;
357 /* The atmel data sheet says the second term is ~rd7 for CP
358 * but that doesn't make any sense. You be the judge. */
359 return (rd & ~rr & ~res) | (~rd & rr & res);
362 static inline int _avr_is_instruction_32_bits(avr_t * avr, uint32_t pc)
364 uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
365 return o == 0x9200 || // STS ! Store Direct to Data Space
366 o == 0x9000 || // LDS Load Direct from Data Space
367 o == 0x940c || // JMP Long Jump
368 o == 0x940d || // JMP Long Jump
369 o == 0x940e || // CALL Long Call to sub
370 o == 0x940f; // CALL Long Call to sub
374 * Main opcode decoder
376 * The decoder was written by following the datasheet in no particular order.
377 * As I went along, I noticed "bit patterns" that could be used to factor opcodes
378 * However, a lot of these only becane apparent later on, so SOME instructions
379 * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
380 * ones scream to be factored).
381 * I assume that the decoder could easily be 2/3 of it's current size.
383 * + It lacks the "extended" XMega jumps.
384 * + It also doesn't check wether the core it's
385 * emulating is suposed to have the fancy instructions, like multiply and such.
387 * for now all instructions take "one" cycle, the cycle+=<extra> needs to be added.
389 uint16_t avr_run_one(avr_t * avr)
392 * this traces spurious reset or bad jump/opcodes and dumps the last 32 "jumps" to track it down
394 if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
400 uint32_t opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
401 uint32_t new_pc = avr->pc + 2; // future "default" pc
404 #if CONFIG_SIMAVR_TRACE
405 avr->touched[0] = avr->touched[1] = avr->touched[2] = 0;
408 switch (opcode & 0xf000) {
411 case 0x0000: { // NOP
415 switch (opcode & 0xfc00) {
416 case 0x0400: { // CPC compare with carry 0000 01rd dddd rrrr
418 uint8_t res = vd - vr - avr->sreg[S_C];
419 STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
422 avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
423 avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
424 avr->sreg[S_N] = (res >> 7) & 1;
425 avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
426 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
429 case 0x0c00: { // ADD without carry 0000 11 rd dddd rrrr
431 uint8_t res = vd + vr;
433 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
435 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
437 _avr_set_r(avr, d, res);
438 avr->sreg[S_Z] = res == 0;
439 avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
440 avr->sreg[S_V] = get_add_overflow(res, vd, vr);
441 avr->sreg[S_N] = (res >> 7) & 1;
442 avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
443 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
446 case 0x0800: { // SBC substract with carry 0000 10rd dddd rrrr
448 uint8_t res = vd - vr - avr->sreg[S_C];
449 STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
450 _avr_set_r(avr, d, res);
453 avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
454 avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
455 avr->sreg[S_N] = (res >> 7) & 1;
456 avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
457 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
461 switch (opcode & 0xff00) {
462 case 0x0100: { // MOVW – Copy Register Word 0000 0001 dddd rrrr
463 uint8_t d = ((opcode >> 4) & 0xf) << 1;
464 uint8_t r = ((opcode) & 0xf) << 1;
465 STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
466 _avr_set_r(avr, d, avr->data[r]);
467 _avr_set_r(avr, d+1, avr->data[r+1]);
469 case 0x0200: { // MULS – Multiply Signed 0000 0010 dddd rrrr
470 int8_t r = opcode & 0xf;
471 int8_t d = (opcode >> 4) & 0xf;
472 int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
473 STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
474 _avr_set_r(avr, 0, res);
475 _avr_set_r(avr, 1, res >> 8);
476 avr->sreg[S_C] = (res >> 15) & 1;
477 avr->sreg[S_Z] = res == 0;
480 case 0x0300: { // multiplications
481 int8_t r = 16 + (opcode & 0x7);
482 int8_t d = 16 + ((opcode >> 4) & 0x7);
485 const char * name = "";
486 switch (opcode & 0x88) {
487 case 0x00: // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
488 res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
492 case 0x08: // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
493 res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
498 case 0x80: // FMULS – Multiply Signed 0000 0011 1ddd 0rrr
499 res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
504 case 0x88: // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 0rrr
505 res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
512 STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
513 _avr_set_r(avr, 0, res);
514 _avr_set_r(avr, 1, res >> 8);
516 avr->sreg[S_Z] = res == 0;
519 default: _avr_invalid_opcode(avr);
527 switch (opcode & 0xfc00) {
528 case 0x1800: { // SUB without carry 0000 10 rd dddd rrrr
530 uint8_t res = vd - vr;
531 STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
532 _avr_set_r(avr, d, res);
533 avr->sreg[S_Z] = res == 0;
534 avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
535 avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
536 avr->sreg[S_N] = (res >> 7) & 1;
537 avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
538 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
541 case 0x1000: { // CPSE Compare, skip if equal 0000 10 rd dddd rrrr
543 uint16_t res = vd == vr;
544 STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":"not ");
546 if (_avr_is_instruction_32_bits(avr, new_pc)) {
547 new_pc += 4; cycle += 2;
549 new_pc += 2; cycle++;
553 case 0x1400: { // CP Compare 0000 10 rd dddd rrrr
555 uint8_t res = vd - vr;
556 STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
557 avr->sreg[S_Z] = res == 0;
558 avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
559 avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
560 avr->sreg[S_N] = res >> 7;
561 avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
562 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
565 case 0x1c00: { // ADD with carry 0001 11 rd dddd rrrr
567 uint8_t res = vd + vr + avr->sreg[S_C];
569 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
571 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
573 _avr_set_r(avr, d, res);
574 avr->sreg[S_Z] = res == 0;
575 avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
576 avr->sreg[S_V] = get_add_overflow(res, vd, vr);
577 avr->sreg[S_N] = (res >> 7) & 1;
578 avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
579 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
582 default: _avr_invalid_opcode(avr);
587 switch (opcode & 0xfc00) {
588 case 0x2000: { // AND 0010 00rd dddd rrrr
590 uint8_t res = vd & vr;
592 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
594 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
596 _avr_set_r(avr, d, res);
597 avr->sreg[S_Z] = res == 0;
598 avr->sreg[S_N] = (res >> 7) & 1;
600 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
603 case 0x2400: { // EOR 0010 01rd dddd rrrr
605 uint8_t res = vd ^ vr;
607 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
609 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
611 _avr_set_r(avr, d, res);
612 avr->sreg[S_Z] = res == 0;
613 avr->sreg[S_N] = (res >> 7) & 1;
615 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
618 case 0x2800: { // OR Logical OR 0010 10rd dddd rrrr
620 uint8_t res = vd | vr;
621 STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
622 _avr_set_r(avr, d, res);
623 avr->sreg[S_Z] = res == 0;
624 avr->sreg[S_N] = (res >> 7) & 1;
626 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
629 case 0x2c00: { // MOV 0010 11rd dddd rrrr
632 STATE("mov %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
633 _avr_set_r(avr, d, res);
635 default: _avr_invalid_opcode(avr);
639 case 0x3000: { // CPI 0011 KKKK rrrr KKKK
641 uint8_t vr = avr->data[r];
642 uint8_t res = vr - k;
643 STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
645 avr->sreg[S_Z] = res == 0;
646 avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
647 avr->sreg[S_V] = get_compare_overflow(res, vr, k);
648 avr->sreg[S_N] = (res >> 7) & 1;
649 avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
650 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
654 case 0x4000: { // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
656 uint8_t vr = avr->data[r];
657 uint8_t res = vr - k - avr->sreg[S_C];
658 STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
659 _avr_set_r(avr, r, res);
660 avr->sreg[S_Z] = res == 0;
661 avr->sreg[S_N] = (res >> 7) & 1;
662 avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
663 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
667 case 0x5000: { // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
669 uint8_t vr = avr->data[r];
670 uint8_t res = vr - k;
671 STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
672 _avr_set_r(avr, r, res);
673 avr->sreg[S_Z] = res == 0;
674 avr->sreg[S_N] = (res >> 7) & 1;
675 avr->sreg[S_C] = k > vr;
676 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
680 case 0x6000: { // ORI aka SBR Logical AND with Immediate 0110 kkkk dddd kkkk
682 uint8_t res = avr->data[r] | k;
683 STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
684 _avr_set_r(avr, r, res);
685 avr->sreg[S_Z] = res == 0;
686 avr->sreg[S_N] = (res >> 7) & 1;
688 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
692 case 0x7000: { // ANDI Logical AND with Immediate 0111 kkkk dddd kkkk
694 uint8_t res = avr->data[r] & k;
695 STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
696 _avr_set_r(avr, r, res);
697 avr->sreg[S_Z] = res == 0;
698 avr->sreg[S_N] = (res >> 7) & 1;
700 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
706 switch (opcode & 0xd008) {
708 case 0x8000: { // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
709 uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
710 uint8_t r = (opcode >> 4) & 0x1f;
711 uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
713 if (opcode & 0x0200) {
714 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
715 _avr_set_ram(avr, v+q, avr->data[r]);
717 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
718 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
723 case 0x8008: { // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
724 uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
725 uint8_t r = (opcode >> 4) & 0x1f;
726 uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
728 if (opcode & 0x0200) {
729 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
730 _avr_set_ram(avr, v+q, avr->data[r]);
732 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
733 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
737 default: _avr_invalid_opcode(avr);
742 /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
743 if ((opcode & 0xff0f) == 0x9408) {
744 uint8_t b = (opcode >> 4) & 7;
745 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
746 avr->sreg[b] = (opcode & 0x0080) == 0;
748 } else switch (opcode) {
749 case 0x9588: { // SLEEP
751 avr->state = cpu_Sleeping;
753 case 0x9598: { // BREAK
756 // if gdb is on, we break here as in here
757 // and we do so until gdb restores the instruction
758 // that was here before
759 avr->state = cpu_StepDone;
764 case 0x95a8: { // WDR
767 case 0x9409: { // IJMP Indirect jump
768 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
769 STATE("ijmp Z[%04x]\n", z << 1);
774 case 0x9509: { // ICALL Indirect Call to Subroutine
775 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
776 STATE("icall Z[%04x]\n", z << 1);
777 _avr_push16(avr, new_pc >> 1);
784 case 0x9508: { // RET
785 new_pc = _avr_pop16(avr) << 1;
786 if (opcode & 0x10) // reti
789 STATE("ret%s\n", opcode & 0x10 ? "i" : "");
793 case 0x95c8: { // LPM Load Program Memory R0 <- (Z)
794 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
795 STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
796 _avr_set_r(avr, 0, avr->flash[z]);
798 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
800 { // BSET 1001 0100 0ddd 1000
801 uint8_t b = (opcode >> 4) & 7;
803 STATE("bset %c\n", _sreg_bit_name[b]);
806 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
808 { // BSET 1001 0100 0ddd 1000
809 uint8_t b = (opcode >> 4) & 7;
811 STATE("bclr %c\n", _sreg_bit_name[b]);
815 switch (opcode & 0xfe0f) {
816 case 0x9000: { // LDS Load Direct from Data Space, 32 bits
817 uint8_t r = (opcode >> 4) & 0x1f;
818 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
820 STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
821 _avr_set_r(avr, r, _avr_get_ram(avr, x));
825 case 0x9004: { // LPM Load Program Memory 1001 000d dddd 01oo
826 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
827 uint8_t r = (opcode >> 4) & 0x1f;
829 STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
830 _avr_set_r(avr, r, avr->flash[z]);
833 _avr_set_r(avr, R_ZH, z >> 8);
834 _avr_set_r(avr, R_ZL, z);
840 case 0x900e: { // LD Load Indirect from Data using X 1001 000r rrrr 11oo
842 uint8_t r = (opcode >> 4) & 0x1f;
843 uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
844 STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
847 _avr_set_r(avr, r, _avr_get_ram(avr, x));
849 _avr_set_r(avr, R_XH, x >> 8);
850 _avr_set_r(avr, R_XL, x);
854 case 0x920e: { // ST Store Indirect Data Space X 1001 001r rrrr 11oo
856 uint8_t r = (opcode >> 4) & 0x1f;
857 uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
858 STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
861 _avr_set_ram(avr, x, avr->data[r]);
863 _avr_set_r(avr, R_XH, x >> 8);
864 _avr_set_r(avr, R_XL, x);
867 case 0x900a: { // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
869 uint8_t r = (opcode >> 4) & 0x1f;
870 uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
871 STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
874 _avr_set_r(avr, r, _avr_get_ram(avr, y));
876 _avr_set_r(avr, R_YH, y >> 8);
877 _avr_set_r(avr, R_YL, y);
880 case 0x920a: { // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
882 uint8_t r = (opcode >> 4) & 0x1f;
883 uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
884 STATE("st %sY[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
887 _avr_set_ram(avr, y, avr->data[r]);
889 _avr_set_r(avr, R_YH, y >> 8);
890 _avr_set_r(avr, R_YL, y);
892 case 0x9200: { // STS ! Store Direct to Data Space, 32 bits
893 uint8_t r = (opcode >> 4) & 0x1f;
894 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
896 STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
897 _avr_set_ram(avr, x, avr->data[r]);
900 case 0x9002: { // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
902 uint8_t r = (opcode >> 4) & 0x1f;
903 uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
904 STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
906 _avr_set_r(avr, r, _avr_get_ram(avr, z));
908 _avr_set_r(avr, R_ZH, z >> 8);
909 _avr_set_r(avr, R_ZL, z);
912 case 0x9202: { // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
914 uint8_t r = (opcode >> 4) & 0x1f;
915 uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
916 STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
918 _avr_set_ram(avr, z, avr->data[r]);
920 _avr_set_r(avr, R_ZH, z >> 8);
921 _avr_set_r(avr, R_ZL, z);
923 case 0x900f: { // POP 1001 000d dddd 1111
924 uint8_t r = (opcode >> 4) & 0x1f;
925 _avr_set_r(avr, r, _avr_pop8(avr));
926 uint16_t sp = _avr_sp_get(avr);
927 STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
930 case 0x920f: { // PUSH 1001 001d dddd 1111
931 uint8_t r = (opcode >> 4) & 0x1f;
932 _avr_push8(avr, avr->data[r]);
933 uint16_t sp = _avr_sp_get(avr);
934 STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
937 case 0x9400: { // COM – One’s Complement
938 uint8_t r = (opcode >> 4) & 0x1f;
939 uint8_t res = 0xff - avr->data[r];
940 STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
941 _avr_set_r(avr, r, res);
942 avr->sreg[S_Z] = res == 0;
943 avr->sreg[S_N] = res >> 7;
946 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
949 case 0x9401: { // NEG – One’s Complement
950 uint8_t r = (opcode >> 4) & 0x1f;
951 uint8_t rd = avr->data[r];
952 uint8_t res = 0x00 - rd;
953 STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
954 _avr_set_r(avr, r, res);
955 avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
956 avr->sreg[S_Z] = res == 0;
957 avr->sreg[S_N] = res >> 7;
958 avr->sreg[S_V] = res == 0x80;
959 avr->sreg[S_C] = res != 0;
960 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
963 case 0x9402: { // SWAP – Swap Nibbles
964 uint8_t r = (opcode >> 4) & 0x1f;
965 uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
966 STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
967 _avr_set_r(avr, r, res);
969 case 0x9403: { // INC – Increment
970 uint8_t r = (opcode >> 4) & 0x1f;
971 uint8_t res = avr->data[r] + 1;
972 STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
973 _avr_set_r(avr, r, res);
974 avr->sreg[S_Z] = res == 0;
975 avr->sreg[S_N] = res >> 7;
976 avr->sreg[S_V] = res == 0x7f;
977 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
980 case 0x9405: { // ASR – Arithmetic Shift Right 1001 010d dddd 0101
981 uint8_t r = (opcode >> 4) & 0x1f;
982 uint8_t vr = avr->data[r];
983 uint8_t res = (vr >> 1) | (vr & 0x80);
984 STATE("asr %s[%02x]\n", avr_regname(r), vr);
985 _avr_set_r(avr, r, res);
986 avr->sreg[S_Z] = res == 0;
987 avr->sreg[S_C] = vr & 1;
988 avr->sreg[S_N] = res >> 7;
989 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
990 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
993 case 0x9406: { // LSR 1001 010d dddd 0110
994 uint8_t r = (opcode >> 4) & 0x1f;
995 uint8_t vr = avr->data[r];
996 uint8_t res = vr >> 1;
997 STATE("lsr %s[%02x]\n", avr_regname(r), vr);
998 _avr_set_r(avr, r, res);
999 avr->sreg[S_Z] = res == 0;
1000 avr->sreg[S_C] = vr & 1;
1002 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1003 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1006 case 0x9407: { // ROR 1001 010d dddd 0111
1007 uint8_t r = (opcode >> 4) & 0x1f;
1008 uint8_t vr = avr->data[r];
1009 uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1010 STATE("ror %s[%02x]\n", avr_regname(r), vr);
1011 _avr_set_r(avr, r, res);
1012 avr->sreg[S_Z] = res == 0;
1013 avr->sreg[S_C] = vr & 1;
1015 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1016 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1019 case 0x940a: { // DEC – Decrement
1020 uint8_t r = (opcode >> 4) & 0x1f;
1021 uint8_t res = avr->data[r] - 1;
1022 STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1023 _avr_set_r(avr, r, res);
1024 avr->sreg[S_Z] = res == 0;
1025 avr->sreg[S_N] = res >> 7;
1026 avr->sreg[S_V] = res == 0x80;
1027 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1031 case 0x940d: { // JMP Long Call to sub, 32 bits
1032 uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1033 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1035 STATE("jmp 0x%06x\n", a);
1041 case 0x940f: { // CALL Long Call to sub, 32 bits
1042 uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1043 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1045 STATE("call 0x%06x\n", a);
1047 _avr_push16(avr, new_pc >> 1);
1049 cycle += 3; // 4 cycles
1055 switch (opcode & 0xff00) {
1056 case 0x9600: { // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1057 uint8_t r = 24 + ((opcode >> 3) & 0x6);
1058 uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1059 uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1060 uint32_t res = rdl | (rdh << 8);
1061 STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1063 _avr_set_r(avr, r + 1, res >> 8);
1064 _avr_set_r(avr, r, res);
1065 avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1066 avr->sreg[S_Z] = (res & 0xffff) == 0;
1067 avr->sreg[S_N] = (res >> 15) & 1;
1068 avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1069 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1073 case 0x9700: { // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1074 uint8_t r = 24 + ((opcode >> 3) & 0x6);
1075 uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1076 uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1077 uint32_t res = rdl | (rdh << 8);
1078 STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1080 _avr_set_r(avr, r + 1, res >> 8);
1081 _avr_set_r(avr, r, res);
1082 avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1083 avr->sreg[S_Z] = (res & 0xffff) == 0;
1084 avr->sreg[S_N] = (res >> 15) & 1;
1085 avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1086 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1090 case 0x9800: { // CBI - Clear Bit in I/O Registe 1001 1000 AAAA Abbb
1091 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1092 uint8_t b = opcode & 0x7;
1093 uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1094 STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1095 _avr_set_ram(avr, io, res);
1098 case 0x9900: { // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1099 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1100 uint8_t b = opcode & 0x7;
1101 uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1102 STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":"not ");
1104 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1105 new_pc += 4; cycle += 2;
1107 new_pc += 2; cycle++;
1111 case 0x9a00: { // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1112 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1113 uint8_t b = opcode & 0x7;
1114 uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1115 STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1116 _avr_set_ram(avr, io, res);
1119 case 0x9b00: { // SBIS - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1120 uint8_t io = (opcode >> 3) & 0x1f;
1121 uint8_t b = opcode & 0x7;
1122 uint8_t res = _avr_get_ram(avr, io + 32) & (1 << b);
1123 STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":"not ");
1125 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1126 new_pc += 4; cycle += 2;
1128 new_pc += 2; cycle++;
1133 switch (opcode & 0xfc00) {
1134 case 0x9c00: { // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1136 uint16_t res = vd * vr;
1137 STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1138 _avr_set_r(avr, 0, res);
1139 _avr_set_r(avr, 1, res >> 8);
1140 avr->sreg[S_Z] = res == 0;
1141 avr->sreg[S_C] = (res >> 15) & 1;
1144 default: _avr_invalid_opcode(avr);
1154 switch (opcode & 0xf800) {
1155 case 0xb800: { // OUT A,Rr 1011 1AAr rrrr AAAA
1156 uint8_t r = (opcode >> 4) & 0x1f;
1157 uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1158 STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1159 // todo: store to IO register
1160 _avr_set_ram(avr, A, avr->data[r]);
1163 case 0xb000: { // IN Rd,A 1011 0AAr rrrr AAAA
1164 uint8_t r = (opcode >> 4) & 0x1f;
1165 uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1166 STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1167 // todo: get the IO register
1168 _avr_set_r(avr, r, _avr_get_ram(avr, A));
1170 default: _avr_invalid_opcode(avr);
1175 // RJMP 1100 kkkk kkkk kkkk
1176 short o = ((short)(opcode << 4)) >> 4;
1177 STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1178 new_pc = new_pc + (o << 1);
1184 // RCALL 1100 kkkk kkkk kkkk
1185 short o = ((short)(opcode << 4)) >> 4;
1186 STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1187 _avr_push16(avr, new_pc >> 1);
1188 new_pc = new_pc + (o << 1);
1190 // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1197 case 0xe000: { // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1198 uint8_t d = 16 + ((opcode >> 4) & 0xf);
1199 uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1200 STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1201 _avr_set_r(avr, d, k);
1205 switch (opcode & 0xfe00) {
1209 case 0xf600: { // All the SREG branches
1210 short o = ((short)(opcode << 6)) >> 9; // offset
1211 uint8_t s = opcode & 7;
1212 int set = (opcode & 0x0400) == 0; // this bit means BRXC otherwise BRXS
1213 int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1214 const char *names[2][8] = {
1215 { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1216 { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1218 if (names[set][s]) {
1219 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1221 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1225 new_pc = new_pc + (o << 1);
1229 case 0xf900: { // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1230 uint8_t r = (opcode >> 4) & 0x1f; // register index
1231 uint8_t s = opcode & 7;
1232 uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1233 STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1234 _avr_set_r(avr, r, v);
1237 case 0xfb00:{ // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1238 uint8_t r = (opcode >> 4) & 0x1f; // register index
1239 uint8_t s = opcode & 7;
1240 STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1241 avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1245 case 0xfe00: { // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1246 uint8_t r = (opcode >> 4) & 0x1f; // register index
1247 uint8_t s = opcode & 7;
1248 int set = (opcode & 0x0200) != 0;
1249 int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1250 STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1252 new_pc = new_pc + 2;
1254 default: _avr_invalid_opcode(avr);
1258 default: _avr_invalid_opcode(avr);
1261 avr->cycle += cycle;