4 Copyright 2008, 2009 Michel Pollet <buserror@gmail.com>
6 This file is part of simavr.
8 simavr is free software: you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation, either version 3 of the License, or
11 (at your option) any later version.
13 simavr is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with simavr. If not, see <http://www.gnu.org/licenses/>.
28 #include "avr_flash.h"
29 #include "avr_watchdog.h"
32 const char * _sreg_bit_name = "cznvshti";
35 * Handle "touching" registers, marking them changed.
36 * This is used only for debugging purposes to be able to
37 * print the effects of each instructions on registers
39 #if CONFIG_SIMAVR_TRACE
40 #define REG_TOUCH(a, r) (a)->touched[(r) >> 5] |= (1 << ((r) & 0x1f))
41 #define REG_ISTOUCHED(a, r) ((a)->touched[(r) >> 5] & (1 << ((r) & 0x1f)))
44 * This allows a "special case" to skip indtruction tracing when in these
45 * symbols. since printf() is useful to have, but generates a lot of cycles
47 int dont_trace(const char * name)
50 !strcmp(name, "uart_putchar") ||
51 !strcmp(name, "fputc") ||
52 !strcmp(name, "printf") ||
53 !strcmp(name, "vfprintf") ||
54 !strcmp(name, "__ultoa_invert") ||
55 !strcmp(name, "__prologue_saves__") ||
56 !strcmp(name, "__epilogue_restores__"));
61 #define STATE(_f, args...) { \
63 if (avr->codeline && avr->codeline[avr->pc>>1]) {\
64 const char * symn = avr->codeline[avr->pc>>1]->symbol; \
65 int dont = 0 && dont_trace(symn);\
66 if (dont!=donttrace) { \
71 printf("%04x: %-25s " _f, avr->pc, symn, ## args);\
73 printf("%s: %04x: " _f, __FUNCTION__, avr->pc, ## args);\
76 #define SREG() if (avr->trace && donttrace == 0) {\
77 printf("%04x: \t\t\t\t\t\t\t\t\tSREG = ", avr->pc); \
78 for (int _sbi = 0; _sbi < 8; _sbi++)\
79 printf("%c", avr->sreg[_sbi] ? toupper(_sreg_bit_name[_sbi]) : '.');\
83 #define REG_TOUCH(a, r)
84 #define STATE(_f, args...)
88 void avr_core_watch_write(avr_t *avr, uint16_t addr, uint8_t v)
90 if (addr > avr->ramend) {
91 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x out of ram\n",
92 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
96 printf("*** Invalid write address PC=%04x SP=%04x O=%04x Address %04x=%02x low registers\n",
97 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, v);
102 * this checks that the current "function" is not doctoring the stack frame that is located
103 * higher on the stack than it should be. It's a sign of code that has overrun it's stack
104 * frame and is munching on it's own return address.
106 if (avr->stack_frame_index > 1 && addr > avr->stack_frame[avr->stack_frame_index-2].sp) {
107 printf("\e[31m%04x : munching stack SP %04x, A=%04x <= %02x\e[0m\n", avr->pc, _avr_sp_get(avr), addr, v);
113 uint8_t avr_core_watch_read(avr_t *avr, uint16_t addr)
115 if (addr > avr->ramend) {
116 printf("*** Invalid read address PC=%04x SP=%04x O=%04x Address %04x out of ram (%04x)\n",
117 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc]<<8), addr, avr->ramend);
120 return avr->data[addr];
124 * Set a register (r < 256)
125 * if it's an IO regisrer (> 31) also (try to) call any callback that was
126 * registered to track changes to that register.
128 static inline void _avr_set_r(avr_t * avr, uint8_t r, uint8_t v)
133 avr->data[R_SREG] = v;
135 for (int i = 0; i < 8; i++)
136 avr->sreg[i] = (v & (1 << i)) != 0;
140 uint8_t io = AVR_DATA_TO_IO(r);
142 avr->io[io].w.c(avr, r, v, avr->io[io].w.param);
145 if (avr->io[io].irq) {
146 avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
147 for (int i = 0; i < 8; i++)
148 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
155 * Stack pointer access
157 inline uint16_t _avr_sp_get(avr_t * avr)
159 return avr->data[R_SPL] | (avr->data[R_SPH] << 8);
162 inline void _avr_sp_set(avr_t * avr, uint16_t sp)
164 _avr_set_r(avr, R_SPL, sp);
165 _avr_set_r(avr, R_SPH, sp >> 8);
169 * Set any address to a value; split between registers and SRAM
171 static inline void _avr_set_ram(avr_t * avr, uint16_t addr, uint8_t v)
174 _avr_set_r(avr, addr, v);
176 avr_core_watch_write(avr, addr, v);
180 * Get a value from SRAM.
182 static inline uint8_t _avr_get_ram(avr_t * avr, uint16_t addr)
184 if (addr == R_SREG) {
186 * SREG is special it's reconstructed when read
187 * while the core itself uses the "shortcut" array
189 avr->data[R_SREG] = 0;
190 for (int i = 0; i < 8; i++)
191 if (avr->sreg[i] > 1) {
192 printf("** Invalid SREG!!\n");
194 } else if (avr->sreg[i])
195 avr->data[R_SREG] |= (1 << i);
197 } else if (addr > 31 && addr < 256) {
198 uint8_t io = AVR_DATA_TO_IO(addr);
201 avr->data[addr] = avr->io[io].r.c(avr, addr, avr->io[io].r.param);
203 if (avr->io[io].irq) {
204 uint8_t v = avr->data[addr];
205 avr_raise_irq(avr->io[io].irq + AVR_IOMEM_IRQ_ALL, v);
206 for (int i = 0; i < 8; i++)
207 avr_raise_irq(avr->io[io].irq + i, (v >> i) & 1);
210 return avr_core_watch_read(avr, addr);
214 * Stack push accessors. Push/pop 8 and 16 bits
216 static inline void _avr_push8(avr_t * avr, uint16_t v)
218 uint16_t sp = _avr_sp_get(avr);
219 _avr_set_ram(avr, sp, v);
220 _avr_sp_set(avr, sp-1);
223 static inline uint8_t _avr_pop8(avr_t * avr)
225 uint16_t sp = _avr_sp_get(avr) + 1;
226 uint8_t res = _avr_get_ram(avr, sp);
227 _avr_sp_set(avr, sp);
231 inline void _avr_push16(avr_t * avr, uint16_t v)
233 _avr_push8(avr, v >> 8);
237 static inline uint16_t _avr_pop16(avr_t * avr)
239 uint16_t res = _avr_pop8(avr);
240 res |= _avr_pop8(avr) << 8;
245 * "Pretty" register names
247 const char * reg_names[255] = {
248 [R_XH] = "XH", [R_XL] = "XL",
249 [R_YH] = "YH", [R_YL] = "YL",
250 [R_ZH] = "ZH", [R_ZL] = "ZL",
251 [R_SPH] = "SPH", [R_SPL] = "SPL",
256 const char * avr_regname(uint8_t reg)
258 if (!reg_names[reg]) {
261 sprintf(tt, "r%d", reg);
263 sprintf(tt, "io:%02x", reg);
264 reg_names[reg] = strdup(tt);
266 return reg_names[reg];
270 * Called when an invalid opcode is decoded
272 static void _avr_invalid_opcode(avr_t * avr)
274 #if CONFIG_SIMAVR_TRACE
275 printf("\e[31m*** %04x: %-25s Invalid Opcode SP=%04x O=%04x \e[0m\n",
276 avr->pc, avr->codeline[avr->pc>>1]->symbol, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
278 printf("\e[31m*** %04x: Invalid Opcode SP=%04x O=%04x \e[0m\n",
279 avr->pc, _avr_sp_get(avr), avr->flash[avr->pc] | (avr->flash[avr->pc+1]<<8));
283 #if CONFIG_SIMAVR_TRACE
285 * Dump changed registers when tracing
287 void avr_dump_state(avr_t * avr)
289 if (!avr->trace || donttrace)
294 for (int r = 0; r < 3 && !doit; r++)
300 const int r16[] = { R_SPL, R_XL, R_YL, R_ZL };
301 for (int i = 0; i < 4; i++)
302 if (REG_ISTOUCHED(avr, r16[i]) || REG_ISTOUCHED(avr, r16[i]+1)) {
303 REG_TOUCH(avr, r16[i]);
304 REG_TOUCH(avr, r16[i]+1);
307 for (int i = 0; i < 3*32; i++)
308 if (REG_ISTOUCHED(avr, i)) {
309 printf("%s=%02x ", avr_regname(i), avr->data[i]);
315 #define get_r_d_10(o) \
316 const uint8_t r = ((o >> 5) & 0x10) | (o & 0xf); \
317 const uint8_t d = (o >> 4) & 0x1f;\
318 const uint8_t vd = avr->data[d], vr = avr->data[r];
319 #define get_k_r16(o) \
320 const uint8_t r = 16 + ((o >> 4) & 0xf); \
321 const uint8_t k = ((o & 0x0f00) >> 4) | (o & 0xf);
324 * Add a "jump" address to the jump trace buffer
326 #if CONFIG_SIMAVR_TRACE
327 #define TRACE_JUMP()\
328 avr->old[avr->old_pci].pc = avr->pc;\
329 avr->old[avr->old_pci].sp = _avr_sp_get(avr);\
330 avr->old_pci = (avr->old_pci + 1) & (OLD_PC_SIZE-1);\
333 #define STACK_FRAME_PUSH()\
334 avr->stack_frame[avr->stack_frame_index].pc = avr->pc;\
335 avr->stack_frame[avr->stack_frame_index].sp = _avr_sp_get(avr);\
336 avr->stack_frame_index++;
337 #define STACK_FRAME_POP()\
338 if (avr->stack_frame_index > 0) \
339 avr->stack_frame_index--;
341 #define STACK_FRAME_PUSH()
342 #define STACK_FRAME_POP()
344 #else /* CONFIG_SIMAVR_TRACE */
347 #define STACK_FRAME_PUSH()
348 #define STACK_FRAME_POP()
352 /****************************************************************************\
354 * Helper functions for calculating the status register bit values.
355 * See the Atmel data sheet for the instruction set for more info.
357 \****************************************************************************/
360 get_add_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
362 uint8_t resb = res >> b & 0x1;
363 uint8_t rdb = rd >> b & 0x1;
364 uint8_t rrb = rr >> b & 0x1;
365 return (rdb & rrb) | (rrb & ~resb) | (~resb & rdb);
369 get_add_overflow (uint8_t res, uint8_t rd, uint8_t rr)
371 uint8_t res7 = res >> 7 & 0x1;
372 uint8_t rd7 = rd >> 7 & 0x1;
373 uint8_t rr7 = rr >> 7 & 0x1;
374 return (rd7 & rr7 & ~res7) | (~rd7 & ~rr7 & res7);
378 get_sub_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
380 uint8_t resb = res >> b & 0x1;
381 uint8_t rdb = rd >> b & 0x1;
382 uint8_t rrb = rr >> b & 0x1;
383 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
387 get_sub_overflow (uint8_t res, uint8_t rd, uint8_t rr)
389 uint8_t res7 = res >> 7 & 0x1;
390 uint8_t rd7 = rd >> 7 & 0x1;
391 uint8_t rr7 = rr >> 7 & 0x1;
392 return (rd7 & ~rr7 & ~res7) | (~rd7 & rr7 & res7);
396 get_compare_carry (uint8_t res, uint8_t rd, uint8_t rr, int b)
398 uint8_t resb = (res >> b) & 0x1;
399 uint8_t rdb = (rd >> b) & 0x1;
400 uint8_t rrb = (rr >> b) & 0x1;
401 return (~rdb & rrb) | (rrb & resb) | (resb & ~rdb);
405 get_compare_overflow (uint8_t res, uint8_t rd, uint8_t rr)
407 res >>= 7; rd >>= 7; rr >>= 7;
408 /* The atmel data sheet says the second term is ~rd7 for CP
409 * but that doesn't make any sense. You be the judge. */
410 return (rd & ~rr & ~res) | (~rd & rr & res);
413 static inline int _avr_is_instruction_32_bits(avr_t * avr, uint32_t pc)
415 uint16_t o = (avr->flash[pc] | (avr->flash[pc+1] << 8)) & 0xfc0f;
416 return o == 0x9200 || // STS ! Store Direct to Data Space
417 o == 0x9000 || // LDS Load Direct from Data Space
418 o == 0x940c || // JMP Long Jump
419 o == 0x940d || // JMP Long Jump
420 o == 0x940e || // CALL Long Call to sub
421 o == 0x940f; // CALL Long Call to sub
425 * Main opcode decoder
427 * The decoder was written by following the datasheet in no particular order.
428 * As I went along, I noticed "bit patterns" that could be used to factor opcodes
429 * However, a lot of these only became apparent later on, so SOME instructions
430 * (skip of bit set etc) are compact, and some could use some refactoring (the ALU
431 * ones scream to be factored).
432 * I assume that the decoder could easily be 2/3 of it's current size.
434 * + It lacks the "extended" XMega jumps.
435 * + It also doesn't check whether the core it's
436 * emulating is supposed to have the fancy instructions, like multiply and such.
438 * for now all instructions take "one" cycle, the cycle+=<extra> needs to be added.
440 uint16_t avr_run_one(avr_t * avr)
442 #if CONFIG_SIMAVR_TRACE
444 * this traces spurious reset or bad jumps
446 if ((avr->pc == 0 && avr->cycle > 0) || avr->pc >= avr->codeend) {
451 avr->touched[0] = avr->touched[1] = avr->touched[2] = 0;
454 uint32_t opcode = (avr->flash[avr->pc + 1] << 8) | avr->flash[avr->pc];
455 uint32_t new_pc = avr->pc + 2; // future "default" pc
458 switch (opcode & 0xf000) {
461 case 0x0000: { // NOP
465 switch (opcode & 0xfc00) {
466 case 0x0400: { // CPC compare with carry 0000 01rd dddd rrrr
468 uint8_t res = vd - vr - avr->sreg[S_C];
469 STATE("cpc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
472 avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
473 avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
474 avr->sreg[S_N] = (res >> 7) & 1;
475 avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
476 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
479 case 0x0c00: { // ADD without carry 0000 11 rd dddd rrrr
481 uint8_t res = vd + vr;
483 STATE("lsl %s[%02x] = %02x\n", avr_regname(d), vd, res & 0xff);
485 STATE("add %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
487 _avr_set_r(avr, d, res);
488 avr->sreg[S_Z] = res == 0;
489 avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
490 avr->sreg[S_V] = get_add_overflow(res, vd, vr);
491 avr->sreg[S_N] = (res >> 7) & 1;
492 avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
493 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
496 case 0x0800: { // SBC substract with carry 0000 10rd dddd rrrr
498 uint8_t res = vd - vr - avr->sreg[S_C];
499 STATE("sbc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
500 _avr_set_r(avr, d, res);
503 avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
504 avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
505 avr->sreg[S_N] = (res >> 7) & 1;
506 avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
507 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
511 switch (opcode & 0xff00) {
512 case 0x0100: { // MOVW – Copy Register Word 0000 0001 dddd rrrr
513 uint8_t d = ((opcode >> 4) & 0xf) << 1;
514 uint8_t r = ((opcode) & 0xf) << 1;
515 STATE("movw %s:%s, %s:%s[%02x%02x]\n", avr_regname(d), avr_regname(d+1), avr_regname(r), avr_regname(r+1), avr->data[r+1], avr->data[r]);
516 _avr_set_r(avr, d, avr->data[r]);
517 _avr_set_r(avr, d+1, avr->data[r+1]);
519 case 0x0200: { // MULS – Multiply Signed 0000 0010 dddd rrrr
520 int8_t r = opcode & 0xf;
521 int8_t d = (opcode >> 4) & 0xf;
522 int16_t res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
523 STATE("muls %s[%d], %s[%02x] = %d\n", avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
524 _avr_set_r(avr, 0, res);
525 _avr_set_r(avr, 1, res >> 8);
526 avr->sreg[S_C] = (res >> 15) & 1;
527 avr->sreg[S_Z] = res == 0;
530 case 0x0300: { // multiplications
531 int8_t r = 16 + (opcode & 0x7);
532 int8_t d = 16 + ((opcode >> 4) & 0x7);
535 const char * name = "";
536 switch (opcode & 0x88) {
537 case 0x00: // MULSU – Multiply Signed Unsigned 0000 0011 0ddd 0rrr
538 res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
542 case 0x08: // FMUL Fractional Multiply Unsigned 0000 0011 0ddd 1rrr
543 res = ((uint8_t)avr->data[r]) * ((uint8_t)avr->data[d]);
548 case 0x80: // FMULS – Multiply Signed 0000 0011 1ddd 0rrr
549 res = ((int8_t)avr->data[r]) * ((int8_t)avr->data[d]);
554 case 0x88: // FMULSU – Multiply Signed Unsigned 0000 0011 1ddd 0rrr
555 res = ((uint8_t)avr->data[r]) * ((int8_t)avr->data[d]);
562 STATE("%s %s[%d], %s[%02x] = %d\n", name, avr_regname(d), ((int8_t)avr->data[d]), avr_regname(r), ((int8_t)avr->data[r]), res);
563 _avr_set_r(avr, 0, res);
564 _avr_set_r(avr, 1, res >> 8);
566 avr->sreg[S_Z] = res == 0;
569 default: _avr_invalid_opcode(avr);
577 switch (opcode & 0xfc00) {
578 case 0x1800: { // SUB without carry 0000 10 rd dddd rrrr
580 uint8_t res = vd - vr;
581 STATE("sub %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
582 _avr_set_r(avr, d, res);
583 avr->sreg[S_Z] = res == 0;
584 avr->sreg[S_H] = get_sub_carry(res, vd, vr, 3);
585 avr->sreg[S_V] = get_sub_overflow(res, vd, vr);
586 avr->sreg[S_N] = (res >> 7) & 1;
587 avr->sreg[S_C] = get_sub_carry(res, vd, vr, 7);
588 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
591 case 0x1000: { // CPSE Compare, skip if equal 0000 10 rd dddd rrrr
593 uint16_t res = vd == vr;
594 STATE("cpse %s[%02x], %s[%02x]\t; Will%s skip\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res ? "":"not ");
596 if (_avr_is_instruction_32_bits(avr, new_pc)) {
597 new_pc += 4; cycle += 2;
599 new_pc += 2; cycle++;
603 case 0x1400: { // CP Compare 0000 10 rd dddd rrrr
605 uint8_t res = vd - vr;
606 STATE("cp %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
607 avr->sreg[S_Z] = res == 0;
608 avr->sreg[S_H] = get_compare_carry(res, vd, vr, 3);
609 avr->sreg[S_V] = get_compare_overflow(res, vd, vr);
610 avr->sreg[S_N] = res >> 7;
611 avr->sreg[S_C] = get_compare_carry(res, vd, vr, 7);
612 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
615 case 0x1c00: { // ADD with carry 0001 11 rd dddd rrrr
617 uint8_t res = vd + vr + avr->sreg[S_C];
619 STATE("rol %s[%02x] = %02x\n", avr_regname(d), avr->data[d], res);
621 STATE("addc %s[%02x], %s[%02x] = %02x\n", avr_regname(d), avr->data[d], avr_regname(r), avr->data[r], res);
623 _avr_set_r(avr, d, res);
624 avr->sreg[S_Z] = res == 0;
625 avr->sreg[S_H] = get_add_carry(res, vd, vr, 3);
626 avr->sreg[S_V] = get_add_overflow(res, vd, vr);
627 avr->sreg[S_N] = (res >> 7) & 1;
628 avr->sreg[S_C] = get_add_carry(res, vd, vr, 7);
629 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
632 default: _avr_invalid_opcode(avr);
637 switch (opcode & 0xfc00) {
638 case 0x2000: { // AND 0010 00rd dddd rrrr
640 uint8_t res = vd & vr;
642 STATE("tst %s[%02x]\n", avr_regname(d), avr->data[d]);
644 STATE("and %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
646 _avr_set_r(avr, d, res);
647 avr->sreg[S_Z] = res == 0;
648 avr->sreg[S_N] = (res >> 7) & 1;
650 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
653 case 0x2400: { // EOR 0010 01rd dddd rrrr
655 uint8_t res = vd ^ vr;
657 STATE("clr %s[%02x]\n", avr_regname(d), avr->data[d]);
659 STATE("eor %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
661 _avr_set_r(avr, d, res);
662 avr->sreg[S_Z] = res == 0;
663 avr->sreg[S_N] = (res >> 7) & 1;
665 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
668 case 0x2800: { // OR Logical OR 0010 10rd dddd rrrr
670 uint8_t res = vd | vr;
671 STATE("or %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
672 _avr_set_r(avr, d, res);
673 avr->sreg[S_Z] = res == 0;
674 avr->sreg[S_N] = (res >> 7) & 1;
676 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
679 case 0x2c00: { // MOV 0010 11rd dddd rrrr
682 STATE("mov %s[%02x], %s[%02x] = %02x\n", avr_regname(d), vd, avr_regname(r), vr, res);
683 _avr_set_r(avr, d, res);
685 default: _avr_invalid_opcode(avr);
689 case 0x3000: { // CPI 0011 KKKK rrrr KKKK
691 uint8_t vr = avr->data[r];
692 uint8_t res = vr - k;
693 STATE("cpi %s[%02x], 0x%02x\n", avr_regname(r), vr, k);
695 avr->sreg[S_Z] = res == 0;
696 avr->sreg[S_H] = get_compare_carry(res, vr, k, 3);
697 avr->sreg[S_V] = get_compare_overflow(res, vr, k);
698 avr->sreg[S_N] = (res >> 7) & 1;
699 avr->sreg[S_C] = get_compare_carry(res, vr, k, 7);
700 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
704 case 0x4000: { // SBCI Subtract Immediate With Carry 0101 10 kkkk dddd kkkk
706 uint8_t vr = avr->data[r];
707 uint8_t res = vr - k - avr->sreg[S_C];
708 STATE("sbci %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
709 _avr_set_r(avr, r, res);
712 avr->sreg[S_N] = (res >> 7) & 1;
713 avr->sreg[S_C] = (k + avr->sreg[S_C]) > vr;
714 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
718 case 0x5000: { // SUB Subtract Immediate 0101 10 kkkk dddd kkkk
720 uint8_t vr = avr->data[r];
721 uint8_t res = vr - k;
722 STATE("subi %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], k, res);
723 _avr_set_r(avr, r, res);
724 avr->sreg[S_Z] = res == 0;
725 avr->sreg[S_N] = (res >> 7) & 1;
726 avr->sreg[S_C] = k > vr;
727 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
731 case 0x6000: { // ORI aka SBR Logical AND with Immediate 0110 kkkk dddd kkkk
733 uint8_t res = avr->data[r] | k;
734 STATE("ori %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
735 _avr_set_r(avr, r, res);
736 avr->sreg[S_Z] = res == 0;
737 avr->sreg[S_N] = (res >> 7) & 1;
739 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
743 case 0x7000: { // ANDI Logical AND with Immediate 0111 kkkk dddd kkkk
745 uint8_t res = avr->data[r] & k;
746 STATE("andi %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], k);
747 _avr_set_r(avr, r, res);
748 avr->sreg[S_Z] = res == 0;
749 avr->sreg[S_N] = (res >> 7) & 1;
751 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
757 switch (opcode & 0xd008) {
759 case 0x8000: { // LD (LDD) – Load Indirect using Z 10q0 qq0r rrrr 0qqq
760 uint16_t v = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
761 uint8_t r = (opcode >> 4) & 0x1f;
762 uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
764 if (opcode & 0x0200) {
765 STATE("st (Z+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
766 _avr_set_ram(avr, v+q, avr->data[r]);
768 STATE("ld %s, (Z+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
769 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
774 case 0x8008: { // LD (LDD) – Load Indirect using Y 10q0 qq0r rrrr 1qqq
775 uint16_t v = avr->data[R_YL] | (avr->data[R_YH] << 8);
776 uint8_t r = (opcode >> 4) & 0x1f;
777 uint8_t q = ((opcode & 0x2000) >> 8) | ((opcode & 0x0c00) >> 7) | (opcode & 0x7);
779 if (opcode & 0x0200) {
780 STATE("st (Y+%d[%04x]), %s[%02x]\n", q, v+q, avr_regname(r), avr->data[r]);
781 _avr_set_ram(avr, v+q, avr->data[r]);
783 STATE("ld %s, (Y+%d[%04x])=[%02x]\n", avr_regname(r), q, v+q, avr->data[v+q]);
784 _avr_set_r(avr, r, _avr_get_ram(avr, v+q));
788 default: _avr_invalid_opcode(avr);
793 /* this is an annoying special case, but at least these lines handle all the SREG set/clear opcodes */
794 if ((opcode & 0xff0f) == 0x9408) {
795 uint8_t b = (opcode >> 4) & 7;
796 STATE("%s%c\n", opcode & 0x0080 ? "cl" : "se", _sreg_bit_name[b]);
797 avr->sreg[b] = (opcode & 0x0080) == 0;
799 } else switch (opcode) {
800 case 0x9588: { // SLEEP
802 avr->state = cpu_Sleeping;
804 case 0x9598: { // BREAK
807 // if gdb is on, we break here as in here
808 // and we do so until gdb restores the instruction
809 // that was here before
810 avr->state = cpu_StepDone;
815 case 0x95a8: { // WDR
817 avr_ioctl(avr, AVR_IOCTL_WATCHDOG_RESET, 0);
819 case 0x95e8: { // SPM
821 avr_ioctl(avr, AVR_IOCTL_FLASH_SPM, 0);
823 case 0x9409: // IJMP Indirect jump 1001 0100 0000 1001
824 case 0x9419: // EIJMP Indirect jump 1001 0100 0001 1001 bit 4 is "indirect"
825 case 0x9509: // ICALL Indirect Call to Subroutine 1001 0101 0000 1001
826 case 0x9519: { // EICALL Indirect Call to Subroutine 1001 0101 0001 1001 bit 8 is "push pc"
827 int e = opcode & 0x10;
828 int p = opcode & 0x100;
830 _avr_invalid_opcode(avr);
831 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
833 z |= avr->data[avr->eind] << 16;
834 STATE("%si%s Z[%04x]\n", e?"e":"", p?"call":"jmp", z << 1);
837 _avr_push16(avr, new_pc >> 1);
844 case 0x9508: { // RET
845 new_pc = _avr_pop16(avr) << 1;
846 if (opcode & 0x10) // reti
849 STATE("ret%s\n", opcode & 0x10 ? "i" : "");
853 case 0x95c8: { // LPM Load Program Memory R0 <- (Z)
854 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
855 STATE("lpm %s, (Z[%04x])\n", avr_regname(0), z);
856 _avr_set_r(avr, 0, avr->flash[z]);
858 case 0x9408:case 0x9418:case 0x9428:case 0x9438:case 0x9448:case 0x9458:case 0x9468:
860 { // BSET 1001 0100 0ddd 1000
861 uint8_t b = (opcode >> 4) & 7;
863 STATE("bset %c\n", _sreg_bit_name[b]);
866 case 0x9488:case 0x9498:case 0x94a8:case 0x94b8:case 0x94c8:case 0x94d8:case 0x94e8:
868 { // BSET 1001 0100 0ddd 1000
869 uint8_t b = (opcode >> 4) & 7;
871 STATE("bclr %c\n", _sreg_bit_name[b]);
875 switch (opcode & 0xfe0f) {
876 case 0x9000: { // LDS Load Direct from Data Space, 32 bits
877 uint8_t r = (opcode >> 4) & 0x1f;
878 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
880 STATE("lds %s[%02x], 0x%04x\n", avr_regname(r), avr->data[r], x);
881 _avr_set_r(avr, r, _avr_get_ram(avr, x));
885 case 0x9004: { // LPM Load Program Memory 1001 000d dddd 01oo
886 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8);
887 uint8_t r = (opcode >> 4) & 0x1f;
889 STATE("lpm %s, (Z[%04x]%s)\n", avr_regname(r), z, opcode?"+":"");
890 _avr_set_r(avr, r, avr->flash[z]);
893 _avr_set_r(avr, R_ZH, z >> 8);
894 _avr_set_r(avr, R_ZL, z);
899 case 0x9007: { // ELPM Extended Load Program Memory 1001 000d dddd 01oo
901 _avr_invalid_opcode(avr);
902 uint16_t z = avr->data[R_ZL] | (avr->data[R_ZH] << 8) | (avr->data[avr->rampz] << 16);
903 uint8_t r = (opcode >> 4) & 0x1f;
905 STATE("elpm %s, (Z[%02x:%04x]%s)\n", avr_regname(r), z >> 16, z&0xffff, opcode?"+":"");
906 _avr_set_r(avr, r, avr->flash[z]);
909 _avr_set_r(avr, avr->rampz, z >> 16);
910 _avr_set_r(avr, R_ZH, z >> 8);
911 _avr_set_r(avr, R_ZL, z);
917 case 0x900e: { // LD Load Indirect from Data using X 1001 000r rrrr 11oo
919 uint8_t r = (opcode >> 4) & 0x1f;
920 uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
921 STATE("ld %s, %sX[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", x, op == 1 ? "++" : "");
924 _avr_set_r(avr, r, _avr_get_ram(avr, x));
926 _avr_set_r(avr, R_XH, x >> 8);
927 _avr_set_r(avr, R_XL, x);
931 case 0x920e: { // ST Store Indirect Data Space X 1001 001r rrrr 11oo
933 uint8_t r = (opcode >> 4) & 0x1f;
934 uint16_t x = (avr->data[R_XH] << 8) | avr->data[R_XL];
935 STATE("st %sX[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", x, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
938 _avr_set_ram(avr, x, avr->data[r]);
940 _avr_set_r(avr, R_XH, x >> 8);
941 _avr_set_r(avr, R_XL, x);
944 case 0x900a: { // LD Load Indirect from Data using Y 1001 000r rrrr 10oo
946 uint8_t r = (opcode >> 4) & 0x1f;
947 uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
948 STATE("ld %s, %sY[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", y, op == 1 ? "++" : "");
951 _avr_set_r(avr, r, _avr_get_ram(avr, y));
953 _avr_set_r(avr, R_YH, y >> 8);
954 _avr_set_r(avr, R_YL, y);
957 case 0x920a: { // ST Store Indirect Data Space Y 1001 001r rrrr 10oo
959 uint8_t r = (opcode >> 4) & 0x1f;
960 uint16_t y = (avr->data[R_YH] << 8) | avr->data[R_YL];
961 STATE("st %sY[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", y, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
964 _avr_set_ram(avr, y, avr->data[r]);
966 _avr_set_r(avr, R_YH, y >> 8);
967 _avr_set_r(avr, R_YL, y);
969 case 0x9200: { // STS ! Store Direct to Data Space, 32 bits
970 uint8_t r = (opcode >> 4) & 0x1f;
971 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
973 STATE("sts 0x%04x, %s[%02x]\n", x, avr_regname(r), avr->data[r]);
974 _avr_set_ram(avr, x, avr->data[r]);
977 case 0x9002: { // LD Load Indirect from Data using Z 1001 001r rrrr 00oo
979 uint8_t r = (opcode >> 4) & 0x1f;
980 uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
981 STATE("ld %s, %sZ[%04x]%s\n", avr_regname(r), op == 2 ? "--" : "", z, op == 1 ? "++" : "");
983 _avr_set_r(avr, r, _avr_get_ram(avr, z));
985 _avr_set_r(avr, R_ZH, z >> 8);
986 _avr_set_r(avr, R_ZL, z);
989 case 0x9202: { // ST Store Indirect Data Space Z 1001 001r rrrr 00oo
991 uint8_t r = (opcode >> 4) & 0x1f;
992 uint16_t z = (avr->data[R_ZH] << 8) | avr->data[R_ZL];
993 STATE("st %sZ[%04x]%s, %s[%02x] \n", op == 2 ? "--" : "", z, op == 1 ? "++" : "", avr_regname(r), avr->data[r]);
995 _avr_set_ram(avr, z, avr->data[r]);
997 _avr_set_r(avr, R_ZH, z >> 8);
998 _avr_set_r(avr, R_ZL, z);
1000 case 0x900f: { // POP 1001 000d dddd 1111
1001 uint8_t r = (opcode >> 4) & 0x1f;
1002 _avr_set_r(avr, r, _avr_pop8(avr));
1003 uint16_t sp = _avr_sp_get(avr);
1004 STATE("pop %s (@%04x)[%02x]\n", avr_regname(r), sp, avr->data[sp]);
1007 case 0x920f: { // PUSH 1001 001d dddd 1111
1008 uint8_t r = (opcode >> 4) & 0x1f;
1009 _avr_push8(avr, avr->data[r]);
1010 uint16_t sp = _avr_sp_get(avr);
1011 STATE("push %s[%02x] (@%04x)\n", avr_regname(r), avr->data[r], sp);
1014 case 0x9400: { // COM – One’s Complement
1015 uint8_t r = (opcode >> 4) & 0x1f;
1016 uint8_t res = 0xff - avr->data[r];
1017 STATE("com %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1018 _avr_set_r(avr, r, res);
1019 avr->sreg[S_Z] = res == 0;
1020 avr->sreg[S_N] = res >> 7;
1023 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1026 case 0x9401: { // NEG – One’s Complement
1027 uint8_t r = (opcode >> 4) & 0x1f;
1028 uint8_t rd = avr->data[r];
1029 uint8_t res = 0x00 - rd;
1030 STATE("neg %s[%02x] = %02x\n", avr_regname(r), rd, res);
1031 _avr_set_r(avr, r, res);
1032 avr->sreg[S_H] = ((res >> 3) | (rd >> 3)) & 1;
1033 avr->sreg[S_Z] = res == 0;
1034 avr->sreg[S_N] = res >> 7;
1035 avr->sreg[S_V] = res == 0x80;
1036 avr->sreg[S_C] = res != 0;
1037 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1040 case 0x9402: { // SWAP – Swap Nibbles
1041 uint8_t r = (opcode >> 4) & 0x1f;
1042 uint8_t res = (avr->data[r] >> 4) | (avr->data[r] << 4) ;
1043 STATE("swap %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1044 _avr_set_r(avr, r, res);
1046 case 0x9403: { // INC – Increment
1047 uint8_t r = (opcode >> 4) & 0x1f;
1048 uint8_t res = avr->data[r] + 1;
1049 STATE("inc %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1050 _avr_set_r(avr, r, res);
1051 avr->sreg[S_Z] = res == 0;
1052 avr->sreg[S_N] = res >> 7;
1053 avr->sreg[S_V] = res == 0x7f;
1054 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1057 case 0x9405: { // ASR – Arithmetic Shift Right 1001 010d dddd 0101
1058 uint8_t r = (opcode >> 4) & 0x1f;
1059 uint8_t vr = avr->data[r];
1060 uint8_t res = (vr >> 1) | (vr & 0x80);
1061 STATE("asr %s[%02x]\n", avr_regname(r), vr);
1062 _avr_set_r(avr, r, res);
1063 avr->sreg[S_Z] = res == 0;
1064 avr->sreg[S_C] = vr & 1;
1065 avr->sreg[S_N] = res >> 7;
1066 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1067 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1070 case 0x9406: { // LSR 1001 010d dddd 0110
1071 uint8_t r = (opcode >> 4) & 0x1f;
1072 uint8_t vr = avr->data[r];
1073 uint8_t res = vr >> 1;
1074 STATE("lsr %s[%02x]\n", avr_regname(r), vr);
1075 _avr_set_r(avr, r, res);
1076 avr->sreg[S_Z] = res == 0;
1077 avr->sreg[S_C] = vr & 1;
1079 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1080 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1083 case 0x9407: { // ROR 1001 010d dddd 0111
1084 uint8_t r = (opcode >> 4) & 0x1f;
1085 uint8_t vr = avr->data[r];
1086 uint8_t res = (avr->sreg[S_C] ? 0x80 : 0) | vr >> 1;
1087 STATE("ror %s[%02x]\n", avr_regname(r), vr);
1088 _avr_set_r(avr, r, res);
1089 avr->sreg[S_Z] = res == 0;
1090 avr->sreg[S_C] = vr & 1;
1092 avr->sreg[S_V] = avr->sreg[S_N] ^ avr->sreg[S_C];
1093 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1096 case 0x940a: { // DEC – Decrement
1097 uint8_t r = (opcode >> 4) & 0x1f;
1098 uint8_t res = avr->data[r] - 1;
1099 STATE("dec %s[%02x] = %02x\n", avr_regname(r), avr->data[r], res);
1100 _avr_set_r(avr, r, res);
1101 avr->sreg[S_Z] = res == 0;
1102 avr->sreg[S_N] = res >> 7;
1103 avr->sreg[S_V] = res == 0x80;
1104 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1108 case 0x940d: { // JMP Long Call to sub, 32 bits
1109 uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1110 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1112 STATE("jmp 0x%06x\n", a);
1118 case 0x940f: { // CALL Long Call to sub, 32 bits
1119 uint32_t a = ((opcode & 0x01f0) >> 3) | (opcode & 1);
1120 uint16_t x = (avr->flash[new_pc+1] << 8) | avr->flash[new_pc];
1122 STATE("call 0x%06x\n", a);
1124 _avr_push16(avr, new_pc >> 1);
1126 cycle += 3; // 4 cycles
1132 switch (opcode & 0xff00) {
1133 case 0x9600: { // ADIW - Add Immediate to Word 1001 0110 KKdd KKKK
1134 uint8_t r = 24 + ((opcode >> 3) & 0x6);
1135 uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1136 uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1137 uint32_t res = rdl | (rdh << 8);
1138 STATE("adiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1140 _avr_set_r(avr, r + 1, res >> 8);
1141 _avr_set_r(avr, r, res);
1142 avr->sreg[S_V] = ~(rdh >> 7) & ((res >> 15) & 1);
1143 avr->sreg[S_Z] = (res & 0xffff) == 0;
1144 avr->sreg[S_N] = (res >> 15) & 1;
1145 avr->sreg[S_C] = ~((res >> 15) & 1) & (rdh >> 7);
1146 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1150 case 0x9700: { // SBIW - Subtract Immediate from Word 1001 0110 KKdd KKKK
1151 uint8_t r = 24 + ((opcode >> 3) & 0x6);
1152 uint8_t k = ((opcode & 0x00c0) >> 2) | (opcode & 0xf);
1153 uint8_t rdl = avr->data[r], rdh = avr->data[r+1];
1154 uint32_t res = rdl | (rdh << 8);
1155 STATE("sbiw %s:%s[%04x], 0x%02x\n", avr_regname(r), avr_regname(r+1), res, k);
1157 _avr_set_r(avr, r + 1, res >> 8);
1158 _avr_set_r(avr, r, res);
1159 avr->sreg[S_V] = (rdh >> 7) & (~(res >> 15) & 1);
1160 avr->sreg[S_Z] = (res & 0xffff) == 0;
1161 avr->sreg[S_N] = (res >> 15) & 1;
1162 avr->sreg[S_C] = ((res >> 15) & 1) & (~rdh >> 7);
1163 avr->sreg[S_S] = avr->sreg[S_N] ^ avr->sreg[S_V];
1167 case 0x9800: { // CBI - Clear Bit in I/O Registe 1001 1000 AAAA Abbb
1168 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1169 uint8_t b = opcode & 0x7;
1170 uint8_t res = _avr_get_ram(avr, io) & ~(1 << b);
1171 STATE("cbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1172 _avr_set_ram(avr, io, res);
1175 case 0x9900: { // SBIC - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1176 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1177 uint8_t b = opcode & 0x7;
1178 uint8_t res = _avr_get_ram(avr, io) & (1 << b);
1179 STATE("sbic %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, !res?"":"not ");
1181 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1182 new_pc += 4; cycle += 2;
1184 new_pc += 2; cycle++;
1188 case 0x9a00: { // SBI - Set Bit in I/O Register 1001 1000 AAAA Abbb
1189 uint8_t io = ((opcode >> 3) & 0x1f) + 32;
1190 uint8_t b = opcode & 0x7;
1191 uint8_t res = _avr_get_ram(avr, io) | (1 << b);
1192 STATE("sbi %s[%04x], 0x%02x = %02x\n", avr_regname(io), avr->data[io], 1<<b, res);
1193 _avr_set_ram(avr, io, res);
1196 case 0x9b00: { // SBIS - Skip if Bit in I/O Register is Cleared 1001 0111 AAAA Abbb
1197 uint8_t io = (opcode >> 3) & 0x1f;
1198 uint8_t b = opcode & 0x7;
1199 uint8_t res = _avr_get_ram(avr, io + 32) & (1 << b);
1200 STATE("sbis %s[%04x], 0x%02x\t; Will%s branch\n", avr_regname(io), avr->data[io], 1<<b, res?"":"not ");
1202 if (_avr_is_instruction_32_bits(avr, new_pc)) {
1203 new_pc += 4; cycle += 2;
1205 new_pc += 2; cycle++;
1210 switch (opcode & 0xfc00) {
1211 case 0x9c00: { // MUL - Multiply Unsigned 1001 11rd dddd rrrr
1213 uint16_t res = vd * vr;
1214 STATE("mul %s[%02x], %s[%02x] = %04x\n", avr_regname(d), vd, avr_regname(r), vr, res);
1215 _avr_set_r(avr, 0, res);
1216 _avr_set_r(avr, 1, res >> 8);
1217 avr->sreg[S_Z] = res == 0;
1218 avr->sreg[S_C] = (res >> 15) & 1;
1221 default: _avr_invalid_opcode(avr);
1231 switch (opcode & 0xf800) {
1232 case 0xb800: { // OUT A,Rr 1011 1AAr rrrr AAAA
1233 uint8_t r = (opcode >> 4) & 0x1f;
1234 uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1235 STATE("out %s, %s[%02x]\n", avr_regname(A), avr_regname(r), avr->data[r]);
1236 _avr_set_ram(avr, A, avr->data[r]);
1238 case 0xb000: { // IN Rd,A 1011 0AAr rrrr AAAA
1239 uint8_t r = (opcode >> 4) & 0x1f;
1240 uint8_t A = ((((opcode >> 9) & 3) << 4) | ((opcode) & 0xf)) + 32;
1241 STATE("in %s, %s[%02x]\n", avr_regname(r), avr_regname(A), avr->data[A]);
1242 _avr_set_r(avr, r, _avr_get_ram(avr, A));
1244 default: _avr_invalid_opcode(avr);
1249 // RJMP 1100 kkkk kkkk kkkk
1250 short o = ((short)(opcode << 4)) >> 4;
1251 STATE("rjmp .%d [%04x]\n", o, new_pc + (o << 1));
1252 new_pc = new_pc + (o << 1);
1258 // RCALL 1100 kkkk kkkk kkkk
1259 short o = ((short)(opcode << 4)) >> 4;
1260 STATE("rcall .%d [%04x]\n", o, new_pc + (o << 1));
1261 _avr_push16(avr, new_pc >> 1);
1262 new_pc = new_pc + (o << 1);
1264 // 'rcall .1' is used as a cheap "push 16 bits of room on the stack"
1271 case 0xe000: { // LDI Rd, K 1110 KKKK RRRR KKKK -- aka SER (LDI r, 0xff)
1272 uint8_t d = 16 + ((opcode >> 4) & 0xf);
1273 uint8_t k = ((opcode & 0x0f00) >> 4) | (opcode & 0xf);
1274 STATE("ldi %s, 0x%02x\n", avr_regname(d), k);
1275 _avr_set_r(avr, d, k);
1279 switch (opcode & 0xfe00) {
1283 case 0xf600: { // All the SREG branches
1284 short o = ((short)(opcode << 6)) >> 9; // offset
1285 uint8_t s = opcode & 7;
1286 int set = (opcode & 0x0400) == 0; // this bit means BRXC otherwise BRXS
1287 int branch = (avr->sreg[s] && set) || (!avr->sreg[s] && !set);
1288 const char *names[2][8] = {
1289 { "brcc", "brne", "brpl", "brvc", NULL, "brhc", "brtc", "brid"},
1290 { "brcs", "breq", "brmi", "brvs", NULL, "brhs", "brts", "brie"},
1292 if (names[set][s]) {
1293 STATE("%s .%d [%04x]\t; Will%s branch\n", names[set][s], o, new_pc + (o << 1), branch ? "":" not");
1295 STATE("%s%c .%d [%04x]\t; Will%s branch\n", set ? "brbs" : "brbc", _sreg_bit_name[s], o, new_pc + (o << 1), branch ? "":" not");
1299 new_pc = new_pc + (o << 1);
1303 case 0xf900: { // BLD – Bit Store from T into a Bit in Register 1111 100r rrrr 0bbb
1304 uint8_t r = (opcode >> 4) & 0x1f; // register index
1305 uint8_t s = opcode & 7;
1306 uint8_t v = avr->data[r] | (avr->sreg[S_T] ? (1 << s) : 0);
1307 STATE("bld %s[%02x], 0x%02x = %02x\n", avr_regname(r), avr->data[r], 1 << s, v);
1308 _avr_set_r(avr, r, v);
1311 case 0xfb00:{ // BST – Bit Store into T from bit in Register 1111 100r rrrr 0bbb
1312 uint8_t r = (opcode >> 4) & 0x1f; // register index
1313 uint8_t s = opcode & 7;
1314 STATE("bst %s[%02x], 0x%02x\n", avr_regname(r), avr->data[r], 1 << s);
1315 avr->sreg[S_T] = (avr->data[r] >> s) & 1;
1319 case 0xfe00: { // SBRS/SBRC – Skip if Bit in Register is Set/Clear 1111 11sr rrrr 0bbb
1320 uint8_t r = (opcode >> 4) & 0x1f; // register index
1321 uint8_t s = opcode & 7;
1322 int set = (opcode & 0x0200) != 0;
1323 int branch = ((avr->data[r] & (1 << s)) && set) || (!(avr->data[r] & (1 << s)) && !set);
1324 STATE("%s %s[%02x], 0x%02x\t; Will%s branch\n", set ? "sbrs" : "sbrc", avr_regname(r), avr->data[r], 1 << s, branch ? "":" not");
1326 new_pc = new_pc + 2;
1328 default: _avr_invalid_opcode(avr);
1332 default: _avr_invalid_opcode(avr);
1335 avr->cycle += cycle;