2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
4 * Routines for control of EMU10K1 chips
6 * Copyright (c) by James Courtier-Dutton <James@superbug.co.uk>
7 * Added support for Audigy 2 Value.
8 * Added EMU 1010 support.
9 * General bug fixes and enhancements.
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License as published by
20 * the Free Software Foundation; either version 2 of the License, or
21 * (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
34 #include <sound/driver.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/interrupt.h>
38 #include <linux/pci.h>
39 #include <linux/slab.h>
40 #include <linux/vmalloc.h>
41 #include <linux/mutex.h>
44 #include <sound/core.h>
45 #include <sound/emu10k1.h>
46 #include <linux/firmware.h>
51 /*************************************************************************
53 *************************************************************************/
55 void snd_emu10k1_voice_init(struct snd_emu10k1 * emu, int ch)
57 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
58 snd_emu10k1_ptr_write(emu, IP, ch, 0);
59 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
60 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
61 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
62 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
63 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
65 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
66 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
67 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
68 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
69 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
70 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
72 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
73 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
74 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
75 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
76 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
77 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
78 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
79 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
81 /*** these are last so OFF prevents writing ***/
82 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
83 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
84 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
85 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
86 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
88 /* Audigy extra stuffs */
90 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
91 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
92 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
93 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
94 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
95 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
96 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
100 static unsigned int spi_dac_init[] = {
124 static int snd_emu10k1_init(struct snd_emu10k1 *emu, int enable_ir, int resume)
126 unsigned int silent_page;
129 /* disable audio and lock cache */
130 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE,
133 /* reset recording buffers */
134 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
135 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
136 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
137 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
138 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
139 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
141 /* disable channel interrupt */
142 outl(0, emu->port + INTE);
143 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
144 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
145 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
146 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
149 /* set SPDIF bypass mode */
150 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
151 /* enable rear left + rear right AC97 slots */
152 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT |
156 /* init envelope engine */
157 for (ch = 0; ch < NUM_G; ch++)
158 snd_emu10k1_voice_init(emu, ch);
160 snd_emu10k1_ptr_write(emu, SPCS0, 0, emu->spdif_bits[0]);
161 snd_emu10k1_ptr_write(emu, SPCS1, 0, emu->spdif_bits[1]);
162 snd_emu10k1_ptr_write(emu, SPCS2, 0, emu->spdif_bits[2]);
164 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
165 /* Hacks for Alice3 to work independent of haP16V driver */
168 //Setup SRCMulti_I2S SamplingRate
169 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
172 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
174 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
175 snd_emu10k1_ptr20_write(emu, SRCSel, 0, 0x14);
176 /* Setup SRCMulti Input Audio Enable */
177 /* Use 0xFFFFFFFF to enable P16V sounds. */
178 snd_emu10k1_ptr20_write(emu, SRCMULTI_ENABLE, 0, 0xFFFFFFFF);
180 /* Enabled Phased (8-channel) P16V playback */
181 outl(0x0201, emu->port + HCFG2);
182 /* Set playback routing. */
183 snd_emu10k1_ptr20_write(emu, CAPTURE_P16V_SOURCE, 0, 0x78e4);
185 if (emu->card_capabilities->ca0108_chip) { /* audigy2 Value */
186 /* Hacks for Alice3 to work independent of haP16V driver */
189 snd_printk(KERN_INFO "Audigy2 value: Special config.\n");
190 //Setup SRCMulti_I2S SamplingRate
191 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
194 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
196 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
197 outl(0x600000, emu->port + 0x20);
198 outl(0x14, emu->port + 0x24);
200 /* Setup SRCMulti Input Audio Enable */
201 outl(0x7b0000, emu->port + 0x20);
202 outl(0xFF000000, emu->port + 0x24);
204 /* Setup SPDIF Out Audio Enable */
205 /* The Audigy 2 Value has a separate SPDIF out,
206 * so no need for a mixer switch
208 outl(0x7a0000, emu->port + 0x20);
209 outl(0xFF000000, emu->port + 0x24);
210 tmp = inl(emu->port + A_IOCFG) & ~0x8; /* Clear bit 3 */
211 outl(tmp, emu->port + A_IOCFG);
213 if (emu->card_capabilities->spi_dac) { /* Audigy 2 ZS Notebook with DAC Wolfson WM8768/WM8568 */
216 size = ARRAY_SIZE(spi_dac_init);
217 for (n = 0; n < size; n++)
218 snd_emu10k1_spi_write(emu, spi_dac_init[n]);
220 snd_emu10k1_ptr20_write(emu, 0x60, 0, 0x10);
223 * GPIO1: Speakers-enabled.
226 * GPIO4: IEC958 Output on.
231 outl(0x76, emu->port + A_IOCFG); /* Windows uses 0x3f76 */
235 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
236 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
237 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
239 silent_page = (emu->silent_page.addr << 1) | MAP_PTI_MASK;
240 for (ch = 0; ch < NUM_G; ch++) {
241 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
242 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
245 if (emu->card_capabilities->emu1010) {
246 outl(HCFG_AUTOMUTE_ASYNC |
248 HCFG_AUDIOENABLE, emu->port + HCFG);
251 * Mute Disable Audio = 0
252 * Lock Tank Memory = 1
253 * Lock Sound Memory = 0
256 } else if (emu->audigy) {
257 if (emu->revision == 4) /* audigy2 */
258 outl(HCFG_AUDIOENABLE |
259 HCFG_AC3ENABLE_CDSPDIF |
260 HCFG_AC3ENABLE_GPSPDIF |
261 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
263 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
264 /* FIXME: Remove all these emu->model and replace it with a card recognition parameter,
265 * e.g. card_capabilities->joystick */
266 } else if (emu->model == 0x20 ||
267 emu->model == 0xc400 ||
268 (emu->model == 0x21 && emu->revision < 6))
269 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
271 // With on-chip joystick
272 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
274 if (enable_ir) { /* enable IR for SB Live */
275 if (emu->card_capabilities->emu1010) {
276 ; /* Disable all access to A_IOCFG for the emu1010 */
277 } else if (emu->audigy) {
278 unsigned int reg = inl(emu->port + A_IOCFG);
279 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
281 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
283 outl(reg, emu->port + A_IOCFG);
285 unsigned int reg = inl(emu->port + HCFG);
286 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
288 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
290 outl(reg, emu->port + HCFG);
294 if (emu->card_capabilities->emu1010) {
295 ; /* Disable all access to A_IOCFG for the emu1010 */
296 } else if (emu->audigy) { /* enable analog output */
297 unsigned int reg = inl(emu->port + A_IOCFG);
298 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
304 static void snd_emu10k1_audio_enable(struct snd_emu10k1 *emu)
307 * Enable the audio bit
309 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
311 /* Enable analog/digital outs on audigy */
312 if (emu->card_capabilities->emu1010) {
313 ; /* Disable all access to A_IOCFG for the emu1010 */
314 } else if (emu->audigy) {
315 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
317 if (emu->card_capabilities->ca0151_chip) { /* audigy2 */
318 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
319 * This has to be done after init ALice3 I2SOut beyond 48KHz.
320 * So, sequence is important. */
321 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
322 } else if (emu->card_capabilities->ca0108_chip) { /* audigy2 value */
323 /* Unmute Analog now. */
324 outl(inl(emu->port + A_IOCFG) | 0x0060, emu->port + A_IOCFG);
326 /* Disable routing from AC97 line out to Front speakers */
327 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
334 /* FIXME: the following routine disables LiveDrive-II !! */
337 tmp = inl(emu->port + HCFG);
338 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
339 outl(tmp|0x800, emu->port + HCFG);
341 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
343 outl(tmp, emu->port + HCFG);
349 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
352 int snd_emu10k1_done(struct snd_emu10k1 * emu)
356 outl(0, emu->port + INTE);
361 for (ch = 0; ch < NUM_G; ch++)
362 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
363 for (ch = 0; ch < NUM_G; ch++) {
364 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
365 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
366 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
367 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
370 /* reset recording buffers */
371 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
372 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
373 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
374 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
375 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
376 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
377 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
378 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
379 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
381 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
383 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
385 /* disable channel interrupt */
386 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
387 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
388 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
389 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
391 /* disable audio and lock cache */
392 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
393 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
398 /*************************************************************************
399 * ECARD functional implementation
400 *************************************************************************/
402 /* In A1 Silicon, these bits are in the HC register */
403 #define HOOKN_BIT (1L << 12)
404 #define HANDN_BIT (1L << 11)
405 #define PULSEN_BIT (1L << 10)
407 #define EC_GDI1 (1 << 13)
408 #define EC_GDI0 (1 << 14)
410 #define EC_NUM_CONTROL_BITS 20
412 #define EC_AC3_DATA_SELN 0x0001L
413 #define EC_EE_DATA_SEL 0x0002L
414 #define EC_EE_CNTRL_SELN 0x0004L
415 #define EC_EECLK 0x0008L
416 #define EC_EECS 0x0010L
417 #define EC_EESDO 0x0020L
418 #define EC_TRIM_CSN 0x0040L
419 #define EC_TRIM_SCLK 0x0080L
420 #define EC_TRIM_SDATA 0x0100L
421 #define EC_TRIM_MUTEN 0x0200L
422 #define EC_ADCCAL 0x0400L
423 #define EC_ADCRSTN 0x0800L
424 #define EC_DACCAL 0x1000L
425 #define EC_DACMUTEN 0x2000L
426 #define EC_LEDN 0x4000L
428 #define EC_SPDIF0_SEL_SHIFT 15
429 #define EC_SPDIF1_SEL_SHIFT 17
430 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
431 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
432 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
433 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
434 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
435 * be incremented any time the EEPROM's
436 * format is changed. */
438 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
440 /* Addresses for special values stored in to EEPROM */
441 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
442 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
443 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
445 #define EC_LAST_PROMFILE_ADDR 0x2f
447 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
448 * can be up to 30 characters in length
449 * and is stored as a NULL-terminated
450 * ASCII string. Any unused bytes must be
451 * filled with zeros */
452 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
455 /* Most of this stuff is pretty self-evident. According to the hardware
456 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
457 * offset problem. Weird.
459 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
463 #define EC_DEFAULT_ADC_GAIN 0xC4C4
464 #define EC_DEFAULT_SPDIF0_SEL 0x0
465 #define EC_DEFAULT_SPDIF1_SEL 0x4
467 /**************************************************************************
468 * @func Clock bits into the Ecard's control latch. The Ecard uses a
469 * control latch will is loaded bit-serially by toggling the Modem control
470 * lines from function 2 on the E8010. This function hides these details
471 * and presents the illusion that we are actually writing to a distinct
475 static void snd_emu10k1_ecard_write(struct snd_emu10k1 * emu, unsigned int value)
477 unsigned short count;
479 unsigned long hc_port;
480 unsigned int hc_value;
482 hc_port = emu->port + HCFG;
483 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
484 outl(hc_value, hc_port);
486 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
488 /* Set up the value */
489 data = ((value & 0x1) ? PULSEN_BIT : 0);
492 outl(hc_value | data, hc_port);
494 /* Clock the shift register */
495 outl(hc_value | data | HANDN_BIT, hc_port);
496 outl(hc_value | data, hc_port);
500 outl(hc_value | HOOKN_BIT, hc_port);
501 outl(hc_value, hc_port);
504 /**************************************************************************
505 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
506 * trim value consists of a 16bit value which is composed of two
507 * 8 bit gain/trim values, one for the left channel and one for the
508 * right channel. The following table maps from the Gain/Attenuation
509 * value in decibels into the corresponding bit pattern for a single
513 static void snd_emu10k1_ecard_setadcgain(struct snd_emu10k1 * emu,
518 /* Enable writing to the TRIM registers */
519 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
521 /* Do it again to insure that we meet hold time requirements */
522 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
524 for (bit = (1 << 15); bit; bit >>= 1) {
527 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
530 value |= EC_TRIM_SDATA;
533 snd_emu10k1_ecard_write(emu, value);
534 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
535 snd_emu10k1_ecard_write(emu, value);
538 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
541 static int snd_emu10k1_ecard_init(struct snd_emu10k1 * emu)
543 unsigned int hc_value;
545 /* Set up the initial settings */
546 emu->ecard_ctrl = EC_RAW_RUN_MODE |
547 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
548 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
550 /* Step 0: Set the codec type in the hardware control register
551 * and enable audio output */
552 hc_value = inl(emu->port + HCFG);
553 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
554 inl(emu->port + HCFG);
556 /* Step 1: Turn off the led and deassert TRIM_CS */
557 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
559 /* Step 2: Calibrate the ADC and DAC */
560 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
562 /* Step 3: Wait for awhile; XXX We can't get away with this
563 * under a real operating system; we'll need to block and wait that
565 snd_emu10k1_wait(emu, 48000);
567 /* Step 4: Switch off the DAC and ADC calibration. Note
568 * That ADC_CAL is actually an inverted signal, so we assert
569 * it here to stop calibration. */
570 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
572 /* Step 4: Switch into run mode */
573 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
575 /* Step 5: Set the analog input gain */
576 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
581 static int snd_emu10k1_cardbus_init(struct snd_emu10k1 * emu)
583 unsigned long special_port;
586 /* Special initialisation routine
587 * before the rest of the IO-Ports become active.
589 special_port = emu->port + 0x38;
590 value = inl(special_port);
591 outl(0x00d00000, special_port);
592 value = inl(special_port);
593 outl(0x00d00001, special_port);
594 value = inl(special_port);
595 outl(0x00d0005f, special_port);
596 value = inl(special_port);
597 outl(0x00d0007f, special_port);
598 value = inl(special_port);
599 outl(0x0090007f, special_port);
600 value = inl(special_port);
602 snd_emu10k1_ptr20_write(emu, TINA2_VOLUME, 0, 0xfefefefe); /* Defaults to 0x30303030 */
606 static int snd_emu1010_load_firmware(struct snd_emu10k1 * emu, const char * filename)
612 const struct firmware *fw_entry;
614 if ((err = request_firmware(&fw_entry, filename, &emu->pci->dev)) != 0) {
615 snd_printk(KERN_ERR "firmware: %s not found. Err=%d\n",filename, err);
618 snd_printk(KERN_INFO "firmware size=0x%zx\n", fw_entry->size);
619 if (fw_entry->size != 0x133a4) {
620 snd_printk(KERN_ERR "firmware: %s wrong size.\n",filename);
624 /* The FPGA is a Xilinx Spartan IIE XC2S50E */
625 /* GPIO7 -> FPGA PGMN
628 * FPGA CONFIG OFF -> FPGA PGMN
630 outl(0x00, emu->port + A_IOCFG); /* Set PGMN low for 1uS. */
632 outl(0x80, emu->port + A_IOCFG); /* Leave bit 7 set during netlist setup. */
633 udelay(100); /* Allow FPGA memory to clean */
634 for(n = 0; n < fw_entry->size; n++) {
635 value=fw_entry->data[n];
636 for(i = 0; i < 8; i++) {
641 outl(reg, emu->port + A_IOCFG);
642 outl(reg | 0x40, emu->port + A_IOCFG);
645 /* After programming, set GPIO bit 4 high again. */
646 outl(0x10, emu->port + A_IOCFG);
649 release_firmware(fw_entry);
653 static int snd_emu10k1_emu1010_init(struct snd_emu10k1 * emu)
659 const char *hana_filename = "emu/hana.fw";
660 const char *dock_filename = "emu/audio_dock.fw";
662 snd_printk(KERN_INFO "emu1010: Special config.\n");
663 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
664 * Lock Sound Memory Cache, Lock Tank Memory Cache,
667 outl(0x0005a00c, emu->port + HCFG);
668 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
669 * Lock Tank Memory Cache,
672 outl(0x0005a004, emu->port + HCFG);
673 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
676 outl(0x0005a000, emu->port + HCFG);
677 /* AC97 2.1, Any 16Meg of 4Gig address, Auto-Mute, EMU32 Slave,
680 outl(0x0005a000, emu->port + HCFG);
682 /* Disable 48Volt power to Audio Dock */
683 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0 );
685 /* ID, should read & 0x7f = 0x55. (Bit 7 is the IRQ bit) */
686 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ® );
687 snd_printdd("reg1=0x%x\n",reg);
689 /* FPGA netlist already present so clear it */
690 /* Return to programming mode */
692 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0x02 );
694 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ® );
695 snd_printdd("reg2=0x%x\n",reg);
697 /* FPGA failed to return to programming mode */
700 snd_printk(KERN_INFO "emu1010: EMU_HANA_ID=0x%x\n",reg);
701 if ((err = snd_emu1010_load_firmware(emu, hana_filename)) != 0) {
702 snd_printk(KERN_INFO "emu1010: Loading Hana Firmware file %s failed\n", hana_filename);
706 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
707 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ® );
709 /* FPGA failed to be programmed */
710 snd_printk(KERN_INFO "emu1010: Loading Hana Firmware file failed, reg=0x%x\n", reg);
714 snd_printk(KERN_INFO "emu1010: Hana Firmware loaded\n");
715 snd_emu1010_fpga_read(emu, EMU_HANA_MAJOR_REV, &tmp );
716 snd_emu1010_fpga_read(emu, EMU_HANA_MINOR_REV, &tmp2 );
717 snd_printk("Hana ver:%d.%d\n",tmp ,tmp2);
718 /* Enable 48Volt power to Audio Dock */
719 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, EMU_HANA_DOCK_PWR_ON );
721 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ® );
722 snd_printk(KERN_INFO "emu1010: Card options=0x%x\n",reg);
723 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ® );
724 snd_printk(KERN_INFO "emu1010: Card options=0x%x\n",reg);
725 snd_emu1010_fpga_read(emu, EMU_HANA_OPTICAL_TYPE, &tmp );
727 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x01 );
728 snd_emu1010_fpga_read(emu, EMU_HANA_ADC_PADS, &tmp );
729 /* Set no attenuation on Audio Dock pads. */
730 snd_emu1010_fpga_write(emu, EMU_HANA_ADC_PADS, 0x00 );
731 emu->emu1010.adc_pads = 0x00;
732 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp );
733 /* Unmute Audio dock DACs, Headphone source DAC-4. */
734 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30 );
735 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12 );
736 snd_emu1010_fpga_read(emu, EMU_HANA_DAC_PADS, &tmp );
738 snd_emu1010_fpga_write(emu, EMU_HANA_DAC_PADS, 0x0f );
739 emu->emu1010.dac_pads = 0x0f;
740 snd_emu1010_fpga_read(emu, EMU_HANA_DOCK_MISC, &tmp );
741 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_MISC, 0x30 );
742 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp );
743 /* SPDIF Format. Set Consumer mode, 24bit, copy enable */
744 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10 );
746 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19 );
748 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c );
749 /* snd_emu1010_fpga_write(emu, 0x09, 0x0f ); // IRQ Enable: All on */
750 /* IRQ Enable: All off */
751 snd_emu1010_fpga_write(emu, EMU_HANA_IRQ_ENABLE, 0x00 );
753 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ® );
754 snd_printk(KERN_INFO "emu1010: Card options3=0x%x\n",reg);
755 /* Default WCLK set to 48kHz. */
756 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x00 );
757 /* Word Clock source, Internal 48kHz x1 */
758 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K );
759 //snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X );
760 /* Audio Dock LEDs. */
761 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12 );
765 snd_emu1010_fpga_link_dst_src_write(emu,
766 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
767 snd_emu1010_fpga_link_dst_src_write(emu,
768 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
769 snd_emu1010_fpga_link_dst_src_write(emu,
770 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT2);
771 snd_emu1010_fpga_link_dst_src_write(emu,
772 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT2);
776 snd_emu1010_fpga_link_dst_src_write(emu,
777 EMU_DST_ALICE2_EMU32_0, EMU_SRC_HAMOA_ADC_LEFT1);
778 snd_emu1010_fpga_link_dst_src_write(emu,
779 EMU_DST_ALICE2_EMU32_1, EMU_SRC_HAMOA_ADC_RIGHT1);
780 snd_emu1010_fpga_link_dst_src_write(emu,
781 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
782 snd_emu1010_fpga_link_dst_src_write(emu,
783 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_RIGHT2);
784 snd_emu1010_fpga_link_dst_src_write(emu,
785 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HAMOA_ADC_LEFT3);
786 snd_emu1010_fpga_link_dst_src_write(emu,
787 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HAMOA_ADC_RIGHT3);
788 snd_emu1010_fpga_link_dst_src_write(emu,
789 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HAMOA_ADC_LEFT4);
790 snd_emu1010_fpga_link_dst_src_write(emu,
791 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HAMOA_ADC_RIGHT4);
795 snd_emu1010_fpga_link_dst_src_write(emu,
796 EMU_DST_ALICE2_EMU32_0, EMU_SRC_DOCK_MIC_A1);
797 snd_emu1010_fpga_link_dst_src_write(emu,
798 EMU_DST_ALICE2_EMU32_1, EMU_SRC_DOCK_MIC_B1);
799 snd_emu1010_fpga_link_dst_src_write(emu,
800 EMU_DST_ALICE2_EMU32_2, EMU_SRC_HAMOA_ADC_LEFT2);
801 snd_emu1010_fpga_link_dst_src_write(emu,
802 EMU_DST_ALICE2_EMU32_3, EMU_SRC_HAMOA_ADC_LEFT2);
803 snd_emu1010_fpga_link_dst_src_write(emu,
804 EMU_DST_ALICE2_EMU32_4, EMU_SRC_DOCK_ADC1_LEFT1);
805 snd_emu1010_fpga_link_dst_src_write(emu,
806 EMU_DST_ALICE2_EMU32_5, EMU_SRC_DOCK_ADC1_RIGHT1);
807 snd_emu1010_fpga_link_dst_src_write(emu,
808 EMU_DST_ALICE2_EMU32_6, EMU_SRC_DOCK_ADC2_LEFT1);
809 snd_emu1010_fpga_link_dst_src_write(emu,
810 EMU_DST_ALICE2_EMU32_7, EMU_SRC_DOCK_ADC2_RIGHT1);
814 snd_emu1010_fpga_link_dst_src_write(emu,
815 EMU_DST_ALICE2_EMU32_4, EMU_SRC_HANA_ADAT);
816 snd_emu1010_fpga_link_dst_src_write(emu,
817 EMU_DST_ALICE2_EMU32_5, EMU_SRC_HANA_ADAT + 1);
818 snd_emu1010_fpga_link_dst_src_write(emu,
819 EMU_DST_ALICE2_EMU32_6, EMU_SRC_HANA_ADAT + 2);
820 snd_emu1010_fpga_link_dst_src_write(emu,
821 EMU_DST_ALICE2_EMU32_7, EMU_SRC_HANA_ADAT + 3);
822 snd_emu1010_fpga_link_dst_src_write(emu,
823 EMU_DST_ALICE2_EMU32_8, EMU_SRC_HANA_ADAT + 4);
824 snd_emu1010_fpga_link_dst_src_write(emu,
825 EMU_DST_ALICE2_EMU32_9, EMU_SRC_HANA_ADAT + 5);
826 snd_emu1010_fpga_link_dst_src_write(emu,
827 EMU_DST_ALICE2_EMU32_A, EMU_SRC_HANA_ADAT + 6);
828 snd_emu1010_fpga_link_dst_src_write(emu,
829 EMU_DST_ALICE2_EMU32_B, EMU_SRC_HANA_ADAT + 7);
830 snd_emu1010_fpga_link_dst_src_write(emu,
831 EMU_DST_ALICE2_EMU32_C, EMU_SRC_DOCK_MIC_A1);
832 snd_emu1010_fpga_link_dst_src_write(emu,
833 EMU_DST_ALICE2_EMU32_D, EMU_SRC_DOCK_MIC_B1);
834 snd_emu1010_fpga_link_dst_src_write(emu,
835 EMU_DST_ALICE2_EMU32_E, EMU_SRC_HAMOA_ADC_LEFT2);
836 snd_emu1010_fpga_link_dst_src_write(emu,
837 EMU_DST_ALICE2_EMU32_F, EMU_SRC_HAMOA_ADC_LEFT2);
839 for (i = 0;i < 0x20; i++ ) {
840 /* AudioDock Elink <- Silence */
841 snd_emu1010_fpga_link_dst_src_write(emu, 0x0100+i, EMU_SRC_SILENCE);
843 for (i = 0;i < 4; i++) {
844 /* Hana SPDIF Out <- Silence */
845 snd_emu1010_fpga_link_dst_src_write(emu, 0x0200+i, EMU_SRC_SILENCE);
847 for (i = 0;i < 7; i++) {
848 /* Hamoa DAC <- Silence */
849 snd_emu1010_fpga_link_dst_src_write(emu, 0x0300+i, EMU_SRC_SILENCE);
851 for (i = 0;i < 7; i++) {
852 /* Hana ADAT Out <- Silence */
853 snd_emu1010_fpga_link_dst_src_write(emu, EMU_DST_HANA_ADAT + i, EMU_SRC_SILENCE);
855 snd_emu1010_fpga_link_dst_src_write(emu,
856 EMU_DST_ALICE_I2S0_LEFT, EMU_SRC_DOCK_ADC1_LEFT1);
857 snd_emu1010_fpga_link_dst_src_write(emu,
858 EMU_DST_ALICE_I2S0_RIGHT, EMU_SRC_DOCK_ADC1_RIGHT1);
859 snd_emu1010_fpga_link_dst_src_write(emu,
860 EMU_DST_ALICE_I2S1_LEFT, EMU_SRC_DOCK_ADC2_LEFT1);
861 snd_emu1010_fpga_link_dst_src_write(emu,
862 EMU_DST_ALICE_I2S1_RIGHT, EMU_SRC_DOCK_ADC2_RIGHT1);
863 snd_emu1010_fpga_link_dst_src_write(emu,
864 EMU_DST_ALICE_I2S2_LEFT, EMU_SRC_DOCK_ADC3_LEFT1);
865 snd_emu1010_fpga_link_dst_src_write(emu,
866 EMU_DST_ALICE_I2S2_RIGHT, EMU_SRC_DOCK_ADC3_RIGHT1);
867 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x01 ); // Unmute all
869 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp );
871 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
872 * Lock Sound Memory Cache, Lock Tank Memory Cache,
875 outl(0x0000a000, emu->port + HCFG);
876 /* AC97 1.03, Any 32Meg of 2Gig address, Auto-Mute, EMU32 Slave,
877 * Lock Sound Memory Cache, Lock Tank Memory Cache,
878 * Un-Mute all codecs.
880 outl(0x0000a001, emu->port + HCFG);
882 /* Initial boot complete. Now patches */
884 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, &tmp );
885 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19 ); /* MIDI Route */
886 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c ); /* Unknown */
887 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_IN, 0x19 ); /* MIDI Route */
888 snd_emu1010_fpga_write(emu, EMU_HANA_MIDI_OUT, 0x0c ); /* Unknown */
889 snd_emu1010_fpga_read(emu, EMU_HANA_SPDIF_MODE, &tmp );
890 snd_emu1010_fpga_write(emu, EMU_HANA_SPDIF_MODE, 0x10 ); /* SPDIF Format spdif (or 0x11 for aes/ebu) */
892 /* Delay to allow Audio Dock to settle */
894 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, &tmp ); /* IRQ Status */
895 snd_emu1010_fpga_read(emu, EMU_HANA_OPTION_CARDS, ® ); /* OPTIONS: Which cards are attached to the EMU */
896 /* FIXME: The loading of this should be able to happen any time,
897 * as the user can plug/unplug it at any time
899 if (reg & (EMU_HANA_OPTION_DOCK_ONLINE | EMU_HANA_OPTION_DOCK_OFFLINE) ) {
900 /* Audio Dock attached */
901 /* Return to Audio Dock programming mode */
902 snd_printk(KERN_INFO "emu1010: Loading Audio Dock Firmware\n");
903 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, EMU_HANA_FPGA_CONFIG_AUDIODOCK );
904 if ((err = snd_emu1010_load_firmware(emu, dock_filename)) != 0) {
907 snd_emu1010_fpga_write(emu, EMU_HANA_FPGA_CONFIG, 0 );
908 snd_emu1010_fpga_read(emu, EMU_HANA_IRQ_STATUS, ® );
909 snd_printk(KERN_INFO "emu1010: EMU_HANA+DOCK_IRQ_STATUS=0x%x\n",reg);
910 /* ID, should read & 0x7f = 0x55 when FPGA programmed. */
911 snd_emu1010_fpga_read(emu, EMU_HANA_ID, ® );
912 snd_printk(KERN_INFO "emu1010: EMU_HANA+DOCK_ID=0x%x\n",reg);
914 /* FPGA failed to be programmed */
915 snd_printk(KERN_INFO "emu1010: Loading Audio Dock Firmware file failed, reg=0x%x\n", reg);
919 snd_printk(KERN_INFO "emu1010: Audio Dock Firmware loaded\n");
920 snd_emu1010_fpga_read(emu, EMU_DOCK_MAJOR_REV, &tmp );
921 snd_emu1010_fpga_read(emu, EMU_DOCK_MINOR_REV, &tmp2 );
922 snd_printk("Audio Dock ver:%d.%d\n",tmp ,tmp2);
925 snd_emu1010_fpga_link_dst_src_write(emu,
926 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32B + 2); /* ALICE2 bus 0xa2 */
927 snd_emu1010_fpga_link_dst_src_write(emu,
928 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32B + 3); /* ALICE2 bus 0xa3 */
929 snd_emu1010_fpga_link_dst_src_write(emu,
930 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 2); /* ALICE2 bus 0xb2 */
931 snd_emu1010_fpga_link_dst_src_write(emu,
932 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 3); /* ALICE2 bus 0xb3 */
934 /* Default outputs */
935 snd_emu1010_fpga_link_dst_src_write(emu,
936 EMU_DST_DOCK_DAC1_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
937 emu->emu1010.output_source[0] = 21;
938 snd_emu1010_fpga_link_dst_src_write(emu,
939 EMU_DST_DOCK_DAC1_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
940 emu->emu1010.output_source[1] = 22;
941 snd_emu1010_fpga_link_dst_src_write(emu,
942 EMU_DST_DOCK_DAC2_LEFT1, EMU_SRC_ALICE_EMU32A + 2);
943 emu->emu1010.output_source[2] = 23;
944 snd_emu1010_fpga_link_dst_src_write(emu,
945 EMU_DST_DOCK_DAC2_RIGHT1, EMU_SRC_ALICE_EMU32A + 3);
946 emu->emu1010.output_source[3] = 24;
947 snd_emu1010_fpga_link_dst_src_write(emu,
948 EMU_DST_DOCK_DAC3_LEFT1, EMU_SRC_ALICE_EMU32A + 4);
949 emu->emu1010.output_source[4] = 25;
950 snd_emu1010_fpga_link_dst_src_write(emu,
951 EMU_DST_DOCK_DAC3_RIGHT1, EMU_SRC_ALICE_EMU32A + 5);
952 emu->emu1010.output_source[5] = 26;
953 snd_emu1010_fpga_link_dst_src_write(emu,
954 EMU_DST_DOCK_DAC4_LEFT1, EMU_SRC_ALICE_EMU32A + 6);
955 emu->emu1010.output_source[6] = 27;
956 snd_emu1010_fpga_link_dst_src_write(emu,
957 EMU_DST_DOCK_DAC4_RIGHT1, EMU_SRC_ALICE_EMU32A + 7);
958 emu->emu1010.output_source[7] = 28;
959 snd_emu1010_fpga_link_dst_src_write(emu,
960 EMU_DST_DOCK_PHONES_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
961 emu->emu1010.output_source[8] = 21;
962 snd_emu1010_fpga_link_dst_src_write(emu,
963 EMU_DST_DOCK_PHONES_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
964 emu->emu1010.output_source[9] = 22;
965 snd_emu1010_fpga_link_dst_src_write(emu,
966 EMU_DST_DOCK_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
967 emu->emu1010.output_source[10] = 21;
968 snd_emu1010_fpga_link_dst_src_write(emu,
969 EMU_DST_DOCK_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
970 emu->emu1010.output_source[11] = 22;
971 snd_emu1010_fpga_link_dst_src_write(emu,
972 EMU_DST_HANA_SPDIF_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
973 emu->emu1010.output_source[12] = 21;
974 snd_emu1010_fpga_link_dst_src_write(emu,
975 EMU_DST_HANA_SPDIF_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
976 emu->emu1010.output_source[13] = 22;
977 snd_emu1010_fpga_link_dst_src_write(emu,
978 EMU_DST_HAMOA_DAC_LEFT1, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
979 emu->emu1010.output_source[14] = 21;
980 snd_emu1010_fpga_link_dst_src_write(emu,
981 EMU_DST_HAMOA_DAC_RIGHT1, EMU_SRC_ALICE_EMU32A + 1);
982 emu->emu1010.output_source[15] = 22;
983 snd_emu1010_fpga_link_dst_src_write(emu,
984 EMU_DST_HANA_ADAT, EMU_SRC_ALICE_EMU32A + 0); /* ALICE2 bus 0xa0 */
985 emu->emu1010.output_source[16] = 21;
986 snd_emu1010_fpga_link_dst_src_write(emu,
987 EMU_DST_HANA_ADAT + 1, EMU_SRC_ALICE_EMU32A + 1);
988 emu->emu1010.output_source[17] = 22;
989 snd_emu1010_fpga_link_dst_src_write(emu,
990 EMU_DST_HANA_ADAT + 2, EMU_SRC_ALICE_EMU32A + 2);
991 emu->emu1010.output_source[18] = 23;
992 snd_emu1010_fpga_link_dst_src_write(emu,
993 EMU_DST_HANA_ADAT + 3, EMU_SRC_ALICE_EMU32A + 3);
994 emu->emu1010.output_source[19] = 24;
995 snd_emu1010_fpga_link_dst_src_write(emu,
996 EMU_DST_HANA_ADAT + 4, EMU_SRC_ALICE_EMU32A + 4);
997 emu->emu1010.output_source[20] = 25;
998 snd_emu1010_fpga_link_dst_src_write(emu,
999 EMU_DST_HANA_ADAT + 5, EMU_SRC_ALICE_EMU32A + 5);
1000 emu->emu1010.output_source[21] = 26;
1001 snd_emu1010_fpga_link_dst_src_write(emu,
1002 EMU_DST_HANA_ADAT + 6, EMU_SRC_ALICE_EMU32A + 6);
1003 emu->emu1010.output_source[22] = 27;
1004 snd_emu1010_fpga_link_dst_src_write(emu,
1005 EMU_DST_HANA_ADAT + 7, EMU_SRC_ALICE_EMU32A + 7);
1006 emu->emu1010.output_source[23] = 28;
1008 /* TEMP: Select SPDIF in/out */
1009 snd_emu1010_fpga_write(emu, EMU_HANA_OPTICAL_TYPE, 0x0); /* Output spdif */
1011 /* TEMP: Select 48kHz SPDIF out */
1012 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x0); /* Mute all */
1013 snd_emu1010_fpga_write(emu, EMU_HANA_DEFCLOCK, 0x0); /* Default fallback clock 48kHz */
1014 /* Word Clock source, Internal 48kHz x1 */
1015 snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K );
1016 //snd_emu1010_fpga_write(emu, EMU_HANA_WCLOCK, EMU_HANA_WCLOCK_INT_48K | EMU_HANA_WCLOCK_4X );
1017 emu->emu1010.internal_clock = 1; /* 48000 */
1018 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_LEDS_2, 0x12);/* Set LEDs on Audio Dock */
1019 snd_emu1010_fpga_write(emu, EMU_HANA_UNMUTE, 0x1); /* Unmute all */
1020 //snd_emu1010_fpga_write(emu, 0x7, 0x0); /* Mute all */
1021 //snd_emu1010_fpga_write(emu, 0x7, 0x1); /* Unmute all */
1022 //snd_emu1010_fpga_write(emu, 0xe, 0x12); /* Set LEDs on Audio Dock */
1027 * Create the EMU10K1 instance
1031 static int alloc_pm_buffer(struct snd_emu10k1 *emu);
1032 static void free_pm_buffer(struct snd_emu10k1 *emu);
1035 static int snd_emu10k1_free(struct snd_emu10k1 *emu)
1037 if (emu->port) { /* avoid access to already used hardware */
1038 snd_emu10k1_fx8010_tram_setup(emu, 0);
1039 snd_emu10k1_done(emu);
1040 /* remove reserved page */
1041 if (emu->reserved_page) {
1042 snd_emu10k1_synth_free(emu, (struct snd_util_memblk *)emu->reserved_page);
1043 emu->reserved_page = NULL;
1045 snd_emu10k1_free_efx(emu);
1047 if (emu->card_capabilities->emu1010) {
1048 /* Disable 48Volt power to Audio Dock */
1049 snd_emu1010_fpga_write(emu, EMU_HANA_DOCK_PWR, 0 );
1052 snd_util_memhdr_free(emu->memhdr);
1053 if (emu->silent_page.area)
1054 snd_dma_free_pages(&emu->silent_page);
1055 if (emu->ptb_pages.area)
1056 snd_dma_free_pages(&emu->ptb_pages);
1057 vfree(emu->page_ptr_table);
1058 vfree(emu->page_addr_table);
1060 free_pm_buffer(emu);
1063 free_irq(emu->irq, emu);
1065 pci_release_regions(emu->pci);
1066 if (emu->card_capabilities->ca0151_chip) /* P16V */
1068 pci_disable_device(emu->pci);
1073 static int snd_emu10k1_dev_free(struct snd_device *device)
1075 struct snd_emu10k1 *emu = device->device_data;
1076 return snd_emu10k1_free(emu);
1079 static struct snd_emu_chip_details emu_chip_details[] = {
1080 /* Audigy 2 Value AC3 out does not work yet. Need to find out how to turn off interpolators.*/
1081 /* Tested by James@superbug.co.uk 3rd July 2005 */
1084 * ADC: Philips 1361T
1088 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10011102,
1089 .driver = "Audigy2", .name = "Audigy 2 Value [SB0400]",
1095 /* Audigy4 (Not PRO) SB0610 */
1096 /* Tested by James@superbug.co.uk 4th April 2006 */
1102 * 3: 0 - Digital Out, 1 - Line in
1110 * A: Green jack sense (Front)
1112 * C: Black jack sense (Rear/Side Right)
1113 * D: Yellow jack sense (Center/LFE/Side Left)
1117 * Digital Out/Line in switch using A_IOCFG bit 3 (0x08)
1121 /* Mic input not tested.
1122 * Analog CD input not tested
1123 * Digital Out not tested.
1125 * Audio output 5.1 working. Side outputs not working.
1127 /* DSP: CA10300-IAT LF
1128 * DAC: Cirrus Logic CS4382-KQZ
1129 * ADC: Philips 1361T
1130 * AC97: Sigmatel STAC9750
1133 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x10211102,
1134 .driver = "Audigy2", .name = "Audigy 4 [SB0610]",
1139 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1141 /* Audigy 2 ZS Notebook Cardbus card.*/
1142 /* Tested by James@superbug.co.uk 22th December 2005 */
1143 /* Audio output 7.1/Headphones working.
1144 * Digital output working. (AC3 not checked, only PCM)
1145 * Audio inputs not tested.
1148 * DAC: Wolfson WM8768/WM8568
1149 * ADC: Wolfson WM8775
1153 {.vendor = 0x1102, .device = 0x0008, .subsystem = 0x20011102,
1154 .driver = "Audigy2", .name = "Audigy 2 ZS Notebook [SB0530]",
1158 .ca_cardbus_chip = 1,
1161 {.vendor = 0x1102, .device = 0x0008,
1162 .driver = "Audigy2", .name = "Audigy 2 Value [Unknown]",
1167 /* Tested by James@superbug.co.uk 8th July 2005. No sound available yet. */
1168 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x40011102,
1169 .driver = "Audigy2", .name = "E-mu 1010 [4001]",
1175 /* Tested by James@superbug.co.uk 3rd July 2005 */
1176 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20071102,
1177 .driver = "Audigy2", .name = "Audigy 4 PRO [SB0380]",
1185 /* Tested by shane-alsa@cm.nu 5th Nov 2005 */
1186 /* The 0x20061102 does have SB0350 written on it
1187 * Just like 0x20021102
1189 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20061102,
1190 .driver = "Audigy2", .name = "Audigy 2 [SB0350b]",
1198 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20021102,
1199 .driver = "Audigy2", .name = "Audigy 2 ZS [SB0350]",
1207 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x20011102,
1208 .driver = "Audigy2", .name = "Audigy 2 ZS [2001]",
1217 /* Tested by James@superbug.co.uk 3rd July 2005 */
1220 * ADC: Philips 1361T
1224 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10071102,
1225 .driver = "Audigy2", .name = "Audigy 2 [SB0240]",
1232 .adc_1361t = 1, /* 24 bit capture instead of 16bit */
1234 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10051102,
1235 .driver = "Audigy2", .name = "Audigy 2 EX [1005]",
1242 /* Dell OEM/Creative Labs Audigy 2 ZS */
1243 /* See ALSA bug#1365 */
1244 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10031102,
1245 .driver = "Audigy2", .name = "Audigy 2 ZS [SB0353]",
1253 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x10021102,
1254 .driver = "Audigy2", .name = "Audigy 2 Platinum [SB0240P]",
1261 .adc_1361t = 1, /* 24 bit capture instead of 16bit. Fixes ALSA bug#324 */
1263 {.vendor = 0x1102, .device = 0x0004, .revision = 0x04,
1264 .driver = "Audigy2", .name = "Audigy 2 [Unknown]",
1271 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00531102,
1272 .driver = "Audigy", .name = "Audigy 1 [SB0090]",
1277 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00521102,
1278 .driver = "Audigy", .name = "Audigy 1 ES [SB0160]",
1284 {.vendor = 0x1102, .device = 0x0004, .subsystem = 0x00511102,
1285 .driver = "Audigy", .name = "Audigy 1 [SB0090]",
1290 {.vendor = 0x1102, .device = 0x0004,
1291 .driver = "Audigy", .name = "Audigy 1 [Unknown]",
1296 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806B1102,
1297 .driver = "EMU10K1", .name = "SBLive! [SB0105]",
1302 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x806A1102,
1303 .driver = "EMU10K1", .name = "SBLive! Value [SB0103]",
1308 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80691102,
1309 .driver = "EMU10K1", .name = "SBLive! Value [SB0101]",
1314 /* Tested by ALSA bug#1680 26th December 2005 */
1315 /* note: It really has SB0220 written on the card. */
1316 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80661102,
1317 .driver = "EMU10K1", .name = "SB Live 5.1 Dell OEM [SB0220]",
1322 /* Tested by Thomas Zehetbauer 27th Aug 2005 */
1323 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80651102,
1324 .driver = "EMU10K1", .name = "SB Live 5.1 [SB0220]",
1329 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x100a1102,
1330 .driver = "EMU10K1", .name = "SB Live 5.1 [SB0220]",
1335 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80641102,
1336 .driver = "EMU10K1", .name = "SB Live 5.1",
1341 /* Tested by alsa bugtrack user "hus" bug #1297 12th Aug 2005 */
1342 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80611102,
1343 .driver = "EMU10K1", .name = "SBLive 5.1 [SB0060]",
1346 .ac97_chip = 2, /* ac97 is optional; both SBLive 5.1 and platinum
1347 * share the same IDs!
1350 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80511102,
1351 .driver = "EMU10K1", .name = "SBLive! Value [CT4850]",
1356 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80401102,
1357 .driver = "EMU10K1", .name = "SBLive! Platinum [CT4760P]",
1361 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80321102,
1362 .driver = "EMU10K1", .name = "SBLive! Value [CT4871]",
1367 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80311102,
1368 .driver = "EMU10K1", .name = "SBLive! Value [CT4831]",
1373 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80281102,
1374 .driver = "EMU10K1", .name = "SBLive! Value [CT4870]",
1379 /* Tested by James@superbug.co.uk 3rd July 2005 */
1380 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80271102,
1381 .driver = "EMU10K1", .name = "SBLive! Value [CT4832]",
1386 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80261102,
1387 .driver = "EMU10K1", .name = "SBLive! Value [CT4830]",
1392 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80231102,
1393 .driver = "EMU10K1", .name = "SB PCI512 [CT4790]",
1398 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x80221102,
1399 .driver = "EMU10K1", .name = "SBLive! Value [CT4780]",
1404 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x40011102,
1405 .driver = "EMU10K1", .name = "E-mu APS [4001]",
1409 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00211102,
1410 .driver = "EMU10K1", .name = "SBLive! [CT4620]",
1415 {.vendor = 0x1102, .device = 0x0002, .subsystem = 0x00201102,
1416 .driver = "EMU10K1", .name = "SBLive! Value [CT4670]",
1421 {.vendor = 0x1102, .device = 0x0002,
1422 .driver = "EMU10K1", .name = "SB Live [Unknown]",
1427 { } /* terminator */
1430 int __devinit snd_emu10k1_create(struct snd_card *card,
1431 struct pci_dev * pci,
1432 unsigned short extin_mask,
1433 unsigned short extout_mask,
1434 long max_cache_bytes,
1437 struct snd_emu10k1 ** remu)
1439 struct snd_emu10k1 *emu;
1442 unsigned char revision;
1443 unsigned int silent_page;
1444 const struct snd_emu_chip_details *c;
1445 static struct snd_device_ops ops = {
1446 .dev_free = snd_emu10k1_dev_free,
1451 /* enable PCI device */
1452 if ((err = pci_enable_device(pci)) < 0)
1455 emu = kzalloc(sizeof(*emu), GFP_KERNEL);
1457 pci_disable_device(pci);
1461 spin_lock_init(&emu->reg_lock);
1462 spin_lock_init(&emu->emu_lock);
1463 spin_lock_init(&emu->voice_lock);
1464 spin_lock_init(&emu->synth_lock);
1465 spin_lock_init(&emu->memblk_lock);
1466 mutex_init(&emu->fx8010.lock);
1467 INIT_LIST_HEAD(&emu->mapped_link_head);
1468 INIT_LIST_HEAD(&emu->mapped_order_link_head);
1472 emu->get_synth_voice = NULL;
1473 /* read revision & serial */
1474 pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
1475 emu->revision = revision;
1476 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
1477 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
1478 snd_printdd("vendor=0x%x, device=0x%x, subsystem_vendor_id=0x%x, subsystem_id=0x%x\n",pci->vendor, pci->device, emu->serial, emu->model);
1480 for (c = emu_chip_details; c->vendor; c++) {
1481 if (c->vendor == pci->vendor && c->device == pci->device) {
1483 if (c->subsystem && (c->subsystem == subsystem) ) {
1487 if (c->subsystem && (c->subsystem != emu->serial) )
1489 if (c->revision && c->revision != emu->revision)
1495 if (c->vendor == 0) {
1496 snd_printk(KERN_ERR "emu10k1: Card not recognised\n");
1498 pci_disable_device(pci);
1501 emu->card_capabilities = c;
1502 if (c->subsystem && !subsystem)
1503 snd_printdd("Sound card name=%s\n", c->name);
1505 snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x. Forced to subsytem=0x%x\n",
1506 c->name, pci->vendor, pci->device, emu->serial, c->subsystem);
1508 snd_printdd("Sound card name=%s, vendor=0x%x, device=0x%x, subsystem=0x%x.\n",
1509 c->name, pci->vendor, pci->device, emu->serial);
1511 if (!*card->id && c->id) {
1513 strlcpy(card->id, c->id, sizeof(card->id));
1515 for (i = 0; i < snd_ecards_limit; i++) {
1516 if (snd_cards[i] && !strcmp(snd_cards[i]->id, card->id))
1519 if (i >= snd_ecards_limit)
1522 if (n >= SNDRV_CARDS)
1524 snprintf(card->id, sizeof(card->id), "%s_%d", c->id, n);
1528 is_audigy = emu->audigy = c->emu10k2_chip;
1530 /* set the DMA transfer mask */
1531 emu->dma_mask = is_audigy ? AUDIGY_DMA_MASK : EMU10K1_DMA_MASK;
1532 if (pci_set_dma_mask(pci, emu->dma_mask) < 0 ||
1533 pci_set_consistent_dma_mask(pci, emu->dma_mask) < 0) {
1534 snd_printk(KERN_ERR "architecture does not support PCI busmaster DMA with mask 0x%lx\n", emu->dma_mask);
1536 pci_disable_device(pci);
1540 emu->gpr_base = A_FXGPREGBASE;
1542 emu->gpr_base = FXGPREGBASE;
1544 if ((err = pci_request_regions(pci, "EMU10K1")) < 0) {
1546 pci_disable_device(pci);
1549 emu->port = pci_resource_start(pci, 0);
1551 if (request_irq(pci->irq, snd_emu10k1_interrupt, IRQF_SHARED,
1556 emu->irq = pci->irq;
1558 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
1559 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1560 32 * 1024, &emu->ptb_pages) < 0) {
1565 emu->page_ptr_table = (void **)vmalloc(emu->max_cache_pages * sizeof(void*));
1566 emu->page_addr_table = (unsigned long*)vmalloc(emu->max_cache_pages * sizeof(unsigned long));
1567 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
1572 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
1573 EMUPAGESIZE, &emu->silent_page) < 0) {
1577 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
1578 if (emu->memhdr == NULL) {
1582 emu->memhdr->block_extra_size = sizeof(struct snd_emu10k1_memblk) -
1583 sizeof(struct snd_util_memblk);
1585 pci_set_master(pci);
1587 emu->fx8010.fxbus_mask = 0x303f;
1588 if (extin_mask == 0)
1589 extin_mask = 0x3fcf;
1590 if (extout_mask == 0)
1591 extout_mask = 0x7fff;
1592 emu->fx8010.extin_mask = extin_mask;
1593 emu->fx8010.extout_mask = extout_mask;
1594 emu->enable_ir = enable_ir;
1596 if (emu->card_capabilities->ecard) {
1597 if ((err = snd_emu10k1_ecard_init(emu)) < 0)
1599 } else if (emu->card_capabilities->ca_cardbus_chip) {
1600 if ((err = snd_emu10k1_cardbus_init(emu)) < 0)
1602 } else if (emu->card_capabilities->emu1010) {
1603 if ((err = snd_emu10k1_emu1010_init(emu)) < 0) {
1604 snd_emu10k1_free(emu);
1608 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
1609 does not support this, it shouldn't do any harm */
1610 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
1613 /* initialize TRAM setup */
1614 emu->fx8010.itram_size = (16 * 1024)/2;
1615 emu->fx8010.etram_pages.area = NULL;
1616 emu->fx8010.etram_pages.bytes = 0;
1619 * Init to 0x02109204 :
1620 * Clock accuracy = 0 (1000ppm)
1621 * Sample Rate = 2 (48kHz)
1622 * Audio Channel = 1 (Left of 2)
1623 * Source Number = 0 (Unspecified)
1624 * Generation Status = 1 (Original for Cat Code 12)
1625 * Cat Code = 12 (Digital Signal Mixer)
1627 * Emphasis = 0 (None)
1628 * CP = 1 (Copyright unasserted)
1629 * AN = 0 (Audio data)
1632 emu->spdif_bits[0] = emu->spdif_bits[1] =
1633 emu->spdif_bits[2] = SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
1634 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
1635 SPCS_GENERATIONSTATUS | 0x00001200 |
1636 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT;
1638 emu->reserved_page = (struct snd_emu10k1_memblk *)
1639 snd_emu10k1_synth_alloc(emu, 4096);
1640 if (emu->reserved_page)
1641 emu->reserved_page->map_locked = 1;
1643 /* Clear silent pages and set up pointers */
1644 memset(emu->silent_page.area, 0, PAGE_SIZE);
1645 silent_page = emu->silent_page.addr << 1;
1646 for (idx = 0; idx < MAXPAGES; idx++)
1647 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
1649 /* set up voice indices */
1650 for (idx = 0; idx < NUM_G; idx++) {
1651 emu->voices[idx].emu = emu;
1652 emu->voices[idx].number = idx;
1655 if ((err = snd_emu10k1_init(emu, enable_ir, 0)) < 0)
1658 if ((err = alloc_pm_buffer(emu)) < 0)
1662 /* Initialize the effect engine */
1663 if ((err = snd_emu10k1_init_efx(emu)) < 0)
1665 snd_emu10k1_audio_enable(emu);
1667 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops)) < 0)
1670 #ifdef CONFIG_PROC_FS
1671 snd_emu10k1_proc_init(emu);
1674 snd_card_set_dev(card, &pci->dev);
1679 snd_emu10k1_free(emu);
1684 static unsigned char saved_regs[] = {
1685 CPF, PTRX, CVCF, VTFT, Z1, Z2, PSST, DSL, CCCA, CCR, CLP,
1686 FXRT, MAPA, MAPB, ENVVOL, ATKHLDV, DCYSUSV, LFOVAL1, ENVVAL,
1687 ATKHLDM, DCYSUSM, LFOVAL2, IP, IFATN, PEFE, FMMOD, TREMFRQ, FM2FRQ2,
1688 TEMPENV, ADCCR, FXWC, MICBA, ADCBA, FXBA,
1689 MICBS, ADCBS, FXBS, CDCS, GPSCS, SPCS0, SPCS1, SPCS2,
1690 SPBYPASS, AC97SLOT, CDSRCS, GPSRCS, ZVSRCS, MICIDX, ADCIDX, FXIDX,
1693 static unsigned char saved_regs_audigy[] = {
1694 A_ADCIDX, A_MICIDX, A_FXWC1, A_FXWC2, A_SAMPLE_RATE,
1695 A_FXRT2, A_SENDAMOUNTS, A_FXRT1,
1699 static int __devinit alloc_pm_buffer(struct snd_emu10k1 *emu)
1703 size = ARRAY_SIZE(saved_regs);
1705 size += ARRAY_SIZE(saved_regs_audigy);
1706 emu->saved_ptr = vmalloc(4 * NUM_G * size);
1707 if (! emu->saved_ptr)
1709 if (snd_emu10k1_efx_alloc_pm_buffer(emu) < 0)
1711 if (emu->card_capabilities->ca0151_chip &&
1712 snd_p16v_alloc_pm_buffer(emu) < 0)
1717 static void free_pm_buffer(struct snd_emu10k1 *emu)
1719 vfree(emu->saved_ptr);
1720 snd_emu10k1_efx_free_pm_buffer(emu);
1721 if (emu->card_capabilities->ca0151_chip)
1722 snd_p16v_free_pm_buffer(emu);
1725 void snd_emu10k1_suspend_regs(struct snd_emu10k1 *emu)
1731 val = emu->saved_ptr;
1732 for (reg = saved_regs; *reg != 0xff; reg++)
1733 for (i = 0; i < NUM_G; i++, val++)
1734 *val = snd_emu10k1_ptr_read(emu, *reg, i);
1736 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
1737 for (i = 0; i < NUM_G; i++, val++)
1738 *val = snd_emu10k1_ptr_read(emu, *reg, i);
1741 emu->saved_a_iocfg = inl(emu->port + A_IOCFG);
1742 emu->saved_hcfg = inl(emu->port + HCFG);
1745 void snd_emu10k1_resume_init(struct snd_emu10k1 *emu)
1747 if (emu->card_capabilities->ecard)
1748 snd_emu10k1_ecard_init(emu);
1749 else if (emu->card_capabilities->ca_cardbus_chip)
1750 snd_emu10k1_cardbus_init(emu);
1751 else if (emu->card_capabilities->emu1010)
1752 snd_emu10k1_emu1010_init(emu);
1754 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
1755 snd_emu10k1_init(emu, emu->enable_ir, 1);
1758 void snd_emu10k1_resume_regs(struct snd_emu10k1 *emu)
1764 snd_emu10k1_audio_enable(emu);
1766 /* resore for spdif */
1768 outl(emu->saved_a_iocfg, emu->port + A_IOCFG);
1769 outl(emu->saved_hcfg, emu->port + HCFG);
1771 val = emu->saved_ptr;
1772 for (reg = saved_regs; *reg != 0xff; reg++)
1773 for (i = 0; i < NUM_G; i++, val++)
1774 snd_emu10k1_ptr_write(emu, *reg, i, *val);
1776 for (reg = saved_regs_audigy; *reg != 0xff; reg++)
1777 for (i = 0; i < NUM_G; i++, val++)
1778 snd_emu10k1_ptr_write(emu, *reg, i, *val);