1 /* Generic Philips CL RC632 Routines
3 * (C) 2005-2006 Harald Welte <laforge@gnumonks.org>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2
10 * as published by the Free Software Foundation
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
27 #include <sys/types.h>
29 #include <librfid/rfid.h>
30 #include <librfid/rfid_asic.h>
31 #include <librfid/rfid_asic_rc632.h>
32 #include <librfid/rfid_reader_cm5121.h>
33 #include <librfid/rfid_layer2_iso14443a.h>
34 #include <librfid/rfid_protocol_mifare_classic.h>
36 #include "rfid_iso14443_common.h"
43 #define RC632_TMO_AUTH1 140
45 #define ENTER() DEBUGP("entering\n")
46 const struct rfid_asic rc632;
48 /* Register and FIFO Access functions */
50 rc632_reg_write(struct rfid_asic_handle *handle,
54 return handle->rath->rat->priv.rc632.fn.reg_write(handle->rath, reg, val);
58 rc632_reg_read(struct rfid_asic_handle *handle,
62 return handle->rath->rat->priv.rc632.fn.reg_read(handle->rath, reg, val);
66 rc632_fifo_write(struct rfid_asic_handle *handle,
71 return handle->rath->rat->priv.rc632.fn.fifo_write(handle->rath,
76 rc632_fifo_read(struct rfid_asic_handle *handle,
80 return handle->rath->rat->priv.rc632.fn.fifo_read(handle->rath, len, buf);
85 rc632_set_bits(struct rfid_asic_handle *handle,
92 ret = rc632_reg_read(handle, reg, &tmp);
96 /* if bits are already set, no need to set them again */
97 if ((tmp & val) == val)
100 return rc632_reg_write(handle, reg, (tmp|val)&0xff);
103 rc632_set_bit_mask(struct rfid_asic_handle *handle,
104 u_int8_t reg, u_int8_t mask, u_int8_t val)
109 ret = rc632_reg_read(handle, reg, &tmp);
113 /* if bits are already like we want them, abort */
114 if ((tmp & mask) == val)
117 return rc632_reg_write(handle, reg, (tmp & ~mask)|(val & mask));
121 rc632_clear_bits(struct rfid_asic_handle *handle,
128 ret = rc632_reg_read(handle, reg, &tmp);
130 DEBUGP("error during reg_read(%p, %d):%d\n",
134 /* if bits are already cleared, no need to clear them again */
135 if ((tmp & val) == 0)
138 return rc632_reg_write(handle, reg, (tmp & ~val)&0xff);
142 rc632_rf_power(struct rfid_asic_handle *handle, int on)
146 return rc632_set_bits(handle, RC632_REG_TX_CONTROL,
147 RC632_TXCTRL_TX1_RF_EN|
148 RC632_TXCTRL_TX2_RF_EN);
150 return rc632_clear_bits(handle, RC632_REG_TX_CONTROL,
151 RC632_TXCTRL_TX1_RF_EN|
152 RC632_TXCTRL_TX2_RF_EN);
156 rc632_power_up(struct rfid_asic_handle *handle)
159 return rc632_clear_bits(handle, RC632_REG_CONTROL,
160 RC632_CONTROL_POWERDOWN);
164 rc632_power_down(struct rfid_asic_handle *handle)
166 return rc632_set_bits(handle, RC632_REG_CONTROL,
167 RC632_CONTROL_POWERDOWN);
170 /* calculate best 8bit prescaler and divisor for given usec timeout */
171 static int best_prescaler(u_int64_t timeout, u_int8_t *prescaler,
174 u_int8_t best_prescaler, best_divisor, i;
175 int64_t smallest_diff;
177 smallest_diff = LLONG_MAX;
180 for (i = 0; i < 21; i++) {
181 u_int64_t clk, tmp_div, res;
183 clk = 13560000 / (1 << i);
184 tmp_div = (clk * timeout) / 1000000;
187 if ((tmp_div > 0xff) || (tmp_div > clk))
190 res = 1000000 / (clk / tmp_div);
191 diff = res - timeout;
196 if (diff < smallest_diff) {
198 best_divisor = tmp_div;
199 smallest_diff = diff;
203 *prescaler = best_prescaler;
204 *divisor = best_divisor;
206 DEBUGP("timeout %u usec, prescaler = %u, divisor = %u\n",
207 timeout, best_prescaler, best_divisor);
213 rc632_timer_set(struct rfid_asic_handle *handle,
217 u_int8_t prescaler, divisor;
219 ret = best_prescaler(timeout, &prescaler, &divisor);
221 ret = rc632_reg_write(handle, RC632_REG_TIMER_CLOCK,
226 ret = rc632_reg_write(handle, RC632_REG_TIMER_CONTROL,
227 RC632_TMR_START_TX_END|RC632_TMR_STOP_RX_BEGIN);
229 /* clear timer irq bit */
230 ret = rc632_set_bits(handle, RC632_REG_INTERRUPT_RQ, RC632_IRQ_TIMER);
232 ret |= rc632_reg_write(handle, RC632_REG_TIMER_RELOAD, divisor);
237 /* Wait until RC632 is idle or TIMER IRQ has happened */
238 static int rc632_wait_idle_timer(struct rfid_asic_handle *handle)
244 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &irq);
245 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &irq);
246 ret = rc632_reg_read(handle, RC632_REG_INTERRUPT_RQ, &irq);
250 /* FIXME: currently we're lazy: If we actually received
251 * something even after the timer expired, we accept it */
252 if (irq & RC632_IRQ_TIMER && !(irq & RC632_IRQ_RX)) {
254 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &foo);
256 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &foo);
261 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
268 /* poll every millisecond */
273 /* Stupid RC632 implementations don't evaluate interrupts but poll the
274 * command register for "status idle" */
276 rc632_wait_idle(struct rfid_asic_handle *handle, u_int64_t timeout)
280 #define USLEEP_PER_CYCLE 128
283 ret = rc632_reg_read(handle, RC632_REG_COMMAND, &cmd);
288 /* FIXME: read second time ?? */
294 rc632_reg_read(handle, RC632_REG_PRIMARY_STATUS, &foo);
296 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &foo);
299 /* Abort after some timeout */
300 if (cycles > timeout*100/USLEEP_PER_CYCLE) {
305 usleep(USLEEP_PER_CYCLE);
312 rc632_transmit(struct rfid_asic_handle *handle,
318 const u_int8_t *cur_buf = buf;
326 ret = rc632_fifo_write(handle, cur_len, cur_buf, 0x03);
330 if (cur_buf == buf) {
331 /* only start transmit first time */
332 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
339 if (cur_buf < buf + len) {
340 cur_len = buf - cur_buf;
348 return rc632_wait_idle(handle, timeout);
352 tcl_toggle_pcb(struct rfid_asic_handle *handle)
354 // FIXME: toggle something between 0x0a and 0x0b
359 rc632_transceive(struct rfid_asic_handle *handle,
360 const u_int8_t *tx_buf,
369 const u_int8_t *cur_tx_buf = tx_buf;
371 DEBUGP("timer = %u\n", timer);
378 ret = rc632_timer_set(handle, timer);
382 ret = rc632_reg_write(handle, RC632_REG_COMMAND, 0x00);
383 /* clear all interrupts */
384 ret = rc632_reg_write(handle, RC632_REG_INTERRUPT_RQ, 0x7f);
387 ret = rc632_fifo_write(handle, cur_tx_len, cur_tx_buf, 0x03);
391 if (cur_tx_buf == tx_buf) {
392 ret = rc632_reg_write(handle, RC632_REG_COMMAND,
393 RC632_CMD_TRANSCEIVE);
398 cur_tx_buf += cur_tx_len;
399 if (cur_tx_buf < tx_buf + tx_len) {
401 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH,
406 cur_tx_len = 64 - fifo_fill;
407 //printf("refilling tx fifo with %u bytes\n", cur_tx_len);
411 } while (cur_tx_len);
414 tcl_toggle_pcb(handle);
416 //ret = rc632_wait_idle_timer(handle);
417 ret = rc632_wait_idle(handle, timer);
421 ret = rc632_reg_read(handle, RC632_REG_FIFO_LENGTH, &rx_avail);
425 if (rx_avail > *rx_len) {
426 //printf("rx_avail(%d) > rx_len(%d), JFYI\n", rx_avail, *rx_len);
427 } else if (*rx_len > rx_avail)
433 DEBUGP("rx_len == 0\n");
435 rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &tmp);
436 rc632_reg_read(handle, RC632_REG_CHANNEL_REDUNDANCY, &tmp);
441 return rc632_fifo_read(handle, *rx_len, rx_buf);
442 /* FIXME: discard addidional bytes in FIFO */
446 rc632_read_eeprom(struct rfid_asic_handle *handle)
448 u_int8_t recvbuf[60];
456 ret = rc632_fifo_write(handle, 3, sndbuf, 0x03);
460 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_READ_E2);
466 ret = rc632_fifo_read(handle, sizeof(recvbuf), recvbuf);
470 // FIXME: do something with eeprom contents
475 rc632_calc_crc16_from(struct rfid_asic_handle *handle)
477 u_int8_t sndbuf[2] = { 0x01, 0x02 };
478 u_int8_t crc_lsb = 0x00 , crc_msb = 0x00;
481 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0x12);
485 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xe0);
489 ret = rc632_fifo_write(handle, sizeof(sndbuf), sndbuf, 3);
493 ret = rc632_reg_write(handle, RC632_REG_COMMAND, RC632_CMD_CALC_CRC);
497 usleep(10000); // FIXME: no checking for cmd completion?
499 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_LSB, &crc_lsb);
503 ret = rc632_reg_read(handle, RC632_REG_CRC_RESULT_MSB, &crc_msb);
507 // FIXME: what to do with crc result?
513 rc632_register_dump(struct rfid_asic_handle *handle, u_int8_t *buf)
518 for (i = 0; i <= 0x3f; i++)
519 ret |= rc632_reg_read(handle, i, &buf[i]);
524 /* generic FIFO access functions (if no more efficient ones provided by
525 * transport driver) */
530 // FIXME: implementation (not needed for CM 5121)
537 // FIXME: implementation (not neded for CM 5121)
542 rc632_init(struct rfid_asic_handle *ah)
546 /* switch off rf (make sure PICCs are reset at init time) */
547 ret = rc632_power_down(ah);
554 ret = rc632_power_up(ah);
558 /* disable register paging */
559 ret = rc632_reg_write(ah, 0x00, 0x00);
563 /* set some sane default values */
564 ret = rc632_reg_write(ah, 0x11, 0x5b);
569 ret = rc632_rf_power(ah, 0);
576 ret = rc632_rf_power(ah, 1);
584 rc632_fini(struct rfid_asic_handle *ah)
589 ret = rc632_rf_power(ah, 0);
593 ret = rc632_power_down(ah);
600 struct rfid_asic_handle *
601 rc632_open(struct rfid_asic_transport_handle *th)
603 struct rfid_asic_handle *h;
605 h = malloc_asic_handle(sizeof(*h));
608 memset(h, 0, sizeof(*h));
610 h->asic = (void*)&rc632;
613 /* FIXME: this is only cm5121 specific, since the latency
614 * down to the RC632 FIFO is too long to refill during TX/RX */
615 h->mtu = h->mru = 64;
617 if (rc632_init(h) < 0) {
626 rc632_close(struct rfid_asic_handle *h)
634 * Philips CL RC632 primitives for ISO 14443-A compliant PICC's
636 * (C) 2005-2006 by Harald Welte <laforge@gnumonks.org>
641 rc632_iso14443a_init(struct rfid_asic_handle *handle)
645 // FIXME: some fifo work (drain fifo?)
647 /* flush fifo (our way) */
648 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
649 RC632_CONTROL_FIFO_FLUSH);
651 ret = rc632_reg_write(handle, RC632_REG_TX_CONTROL,
652 (RC632_TXCTRL_TX1_RF_EN |
653 RC632_TXCTRL_TX2_RF_EN |
654 RC632_TXCTRL_TX2_INV |
655 RC632_TXCTRL_FORCE_100_ASK |
656 RC632_TXCTRL_MOD_SRC_INT));
660 ret = rc632_reg_write(handle, RC632_REG_CW_CONDUCTANCE,
661 CM5121_CW_CONDUCTANCE);
665 /* Since FORCE_100_ASK is set (cf mc073930.pdf), this line may be left out? */
666 ret = rc632_reg_write(handle, RC632_REG_MOD_CONDUCTANCE,
667 CM5121_MOD_CONDUCTANCE);
671 ret = rc632_reg_write(handle, RC632_REG_CODER_CONTROL,
672 (RC632_CDRCTRL_TXCD_14443A |
673 RC632_CDRCTRL_RATE_106K));
677 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH, 0x13);
681 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH_SOF, 0x3f);
685 ret = rc632_reg_write(handle, RC632_REG_TYPE_B_FRAMING, 0x00);
689 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL1,
690 (RC632_RXCTRL1_GAIN_35DB |
691 RC632_RXCTRL1_ISO14443 |
692 RC632_RXCTRL1_SUBCP_8));
696 ret = rc632_reg_write(handle, RC632_REG_DECODER_CONTROL,
697 (RC632_DECCTRL_MANCHESTER |
698 RC632_DECCTRL_RXFR_14443A));
702 ret = rc632_reg_write(handle, RC632_REG_BIT_PHASE,
703 CM5121_14443A_BITPHASE);
707 ret = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
708 CM5121_14443A_THRESHOLD);
712 ret = rc632_reg_write(handle, RC632_REG_BPSK_DEM_CONTROL, 0x00);
716 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL2,
717 (RC632_RXCTRL2_DECSRC_INT |
718 RC632_RXCTRL2_CLK_Q));
722 /* Omnikey proprietary driver has 0x03, but 0x06 is the default reset value ?!? */
723 ret = rc632_reg_write(handle, RC632_REG_RX_WAIT, 0x06);
727 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
728 (RC632_CR_PARITY_ENABLE |
729 RC632_CR_PARITY_ODD));
733 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0x63);
737 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0x63);
745 rc632_iso14443a_fini(struct iso14443a_handle *handle_14443)
749 ret = rc632_rf_power(handle, 0);
759 /* issue a 14443-3 A PCD -> PICC command in a short frame, such as REQA, WUPA */
761 rc632_iso14443a_transceive_sf(struct rfid_asic_handle *handle,
763 struct iso14443a_atqa *atqa)
770 memset(atqa, 0, sizeof(*atqa));
774 /* transfer only 7 bits of last byte in frame */
775 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x07);
779 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
780 RC632_CONTROL_CRYPTO1_ON);
785 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
786 (RC632_CR_PARITY_ENABLE |
787 RC632_CR_PARITY_ODD));
789 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
790 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
796 ret = rc632_transceive(handle, tx_buf, sizeof(tx_buf),
797 (u_int8_t *)atqa, &rx_len,
798 ISO14443A_FDT_ANTICOL_LAST1, 0);
800 DEBUGP("error during rc632_transceive()\n");
804 /* switch back to normal 8bit last byte */
805 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING, 0x00);
809 /* determine whether there was a collission */
810 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
814 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
816 /* retrieve bit of collission */
817 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
820 DEBUGP("collision detected in xcv_sf: bit_of_col=%u\n", boc);
821 /* FIXME: how to signal this up the stack */
825 DEBUGP("rx_len(%d) != 2\n", rx_len);
832 /* transceive regular frame */
834 rc632_iso14443ab_transceive(struct rfid_asic_handle *handle,
835 unsigned int frametype,
836 const u_int8_t *tx_buf, unsigned int tx_len,
837 u_int8_t *rx_buf, unsigned int *rx_len,
838 u_int64_t timeout, unsigned int flags)
842 u_int8_t channel_red;
849 memset(rx_buf, 0, *rx_len);
852 case RFID_14443A_FRAME_REGULAR:
853 case RFID_MIFARE_FRAME:
854 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
855 |RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
857 case RFID_14443B_FRAME_REGULAR:
858 channel_red = RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE
862 case RFID_MIFARE_FRAME:
863 channel_red = RC632_CR_PARITY_ENABLE|RC632_CR_PARITY_ODD;
870 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
875 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, timeout, 0);
884 /* transceive anti collission bitframe */
886 rc632_iso14443a_transceive_acf(struct rfid_asic_handle *handle,
887 struct iso14443a_anticol_cmd *acf,
888 unsigned int *bit_of_col)
892 u_int8_t rx_len = sizeof(rx_buf);
893 u_int8_t rx_align = 0, tx_last_bits, tx_bytes, tx_bytes_total;
896 *bit_of_col = ISO14443A_BITOFCOL_NONE;
897 memset(rx_buf, 0, sizeof(rx_buf));
899 /* disable mifare cryto */
900 ret = rc632_clear_bits(handle, RC632_REG_CONTROL,
901 RC632_CONTROL_CRYPTO1_ON);
905 /* disable CRC summing */
907 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
908 (RC632_CR_PARITY_ENABLE |
909 RC632_CR_PARITY_ODD));
911 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
912 RC632_CR_TX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
917 tx_last_bits = acf->nvb & 0x07; /* lower nibble indicates bits */
918 tx_bytes = ( acf->nvb >> 4 ) & 0x07;
920 tx_bytes_total = tx_bytes+1;
921 rx_align = tx_last_bits & 0x07; /* rx frame complements tx */
924 tx_bytes_total = tx_bytes;
926 /* set RxAlign and TxLastBits*/
927 ret = rc632_reg_write(handle, RC632_REG_BIT_FRAMING,
928 (rx_align << 4) | (tx_last_bits));
932 ret = rc632_transceive(handle, (u_int8_t *)acf, tx_bytes_total,
933 rx_buf, &rx_len, 0x32, 0);
937 /* bitwise-OR the two halves of the split byte */
938 acf->uid_bits[tx_bytes-2] = (
939 (acf->uid_bits[tx_bytes-2] & (0xff >> (8-tx_last_bits)))
944 memcpy(&acf->uid_bits[tx_bytes-1], &rx_buf[1], rx_len-1);
946 /* determine whether there was a collission */
947 ret = rc632_reg_read(handle, RC632_REG_ERROR_FLAG, &error_flag);
951 if (error_flag & RC632_ERR_FLAG_COL_ERR) {
952 /* retrieve bit of collission */
953 ret = rc632_reg_read(handle, RC632_REG_COLL_POS, &boc);
957 /* bit of collission relative to start of part 1 of
958 * anticollision frame (!) */
959 *bit_of_col = 2*8 + boc;
966 RC632_RATE_106 = 0x00,
967 RC632_RATE_212 = 0x01,
968 RC632_RATE_424 = 0x02,
969 RC632_RATE_848 = 0x03,
973 u_int8_t subc_pulses;
975 u_int8_t rx_threshold;
976 u_int8_t bpsk_dem_ctrl;
984 static struct rx_config rx_configs[] = {
986 .subc_pulses = RC632_RXCTRL1_SUBCP_8,
987 .rx_coding = RC632_DECCTRL_MANCHESTER,
988 .rx_threshold = 0x88,
989 .bpsk_dem_ctrl = 0x00,
992 .subc_pulses = RC632_RXCTRL1_SUBCP_4,
993 .rx_coding = RC632_DECCTRL_BPSK,
994 .rx_threshold = 0x50,
995 .bpsk_dem_ctrl = 0x0c,
998 .subc_pulses = RC632_RXCTRL1_SUBCP_2,
999 .rx_coding = RC632_DECCTRL_BPSK,
1000 .rx_threshold = 0x50,
1001 .bpsk_dem_ctrl = 0x0c,
1004 .subc_pulses = RC632_RXCTRL1_SUBCP_1,
1005 .rx_coding = RC632_DECCTRL_BPSK,
1006 .rx_threshold = 0x50,
1007 .bpsk_dem_ctrl = 0x0c,
1011 static struct tx_config tx_configs[] = {
1013 .rate = RC632_CDRCTRL_RATE_106K,
1017 .rate = RC632_CDRCTRL_RATE_212K,
1021 .rate = RC632_CDRCTRL_RATE_424K,
1025 .rate = RC632_CDRCTRL_RATE_848K,
1030 static int rc632_iso14443a_set_speed(struct rfid_asic_handle *handle,
1031 unsigned int tx, unsigned int rate)
1039 if (rate > ARRAY_SIZE(rx_configs))
1042 rc = rc632_set_bit_mask(handle, RC632_REG_RX_CONTROL1,
1043 RC632_RXCTRL1_SUBCP_MASK,
1044 rx_configs[rate].subc_pulses);
1048 rc = rc632_set_bit_mask(handle, RC632_REG_DECODER_CONTROL,
1050 rx_configs[rate].rx_coding);
1054 rc = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1055 rx_configs[rate].rx_threshold);
1059 if (rx_configs[rate].rx_coding == RC632_DECCTRL_BPSK) {
1060 rc = rc632_reg_write(handle,
1061 RC632_REG_BPSK_DEM_CONTROL,
1062 rx_configs[rate].bpsk_dem_ctrl);
1068 if (rate > ARRAY_SIZE(tx_configs))
1071 rc = rc632_set_bit_mask(handle, RC632_REG_CODER_CONTROL,
1072 RC632_CDRCTRL_RATE_MASK,
1073 tx_configs[rate].rate);
1077 rc = rc632_reg_write(handle, RC632_REG_MOD_WIDTH,
1078 tx_configs[rate].mod_width);
1086 static int rc632_iso14443b_init(struct rfid_asic_handle *handle)
1090 // FIXME: some FIFO work
1092 /* flush fifo (our way) */
1093 ret = rc632_reg_write(handle, RC632_REG_CONTROL,
1094 RC632_CONTROL_FIFO_FLUSH);
1098 ret = rc632_reg_write(handle, RC632_REG_TX_CONTROL,
1099 (RC632_TXCTRL_TX1_RF_EN |
1100 RC632_TXCTRL_TX2_RF_EN |
1101 RC632_TXCTRL_TX2_INV |
1102 RC632_TXCTRL_MOD_SRC_INT));
1106 ret = rc632_reg_write(handle, RC632_REG_CW_CONDUCTANCE, 0x3f);
1110 ret = rc632_reg_write(handle, RC632_REG_MOD_CONDUCTANCE, 0x04);
1114 ret = rc632_reg_write(handle, RC632_REG_CODER_CONTROL,
1115 (RC632_CDRCTRL_TXCD_NRZ |
1116 RC632_CDRCTRL_RATE_14443B));
1120 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH, 0x13);
1124 ret = rc632_reg_write(handle, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1128 ret = rc632_reg_write(handle, RC632_REG_TYPE_B_FRAMING,
1129 (RC632_TBFRAMING_SOF_11L_3H |
1130 (6 << RC632_TBFRAMING_SPACE_SHIFT) |
1131 RC632_TBFRAMING_EOF_11));
1135 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL1,
1136 (RC632_RXCTRL1_GAIN_35DB |
1137 RC632_RXCTRL1_ISO14443 |
1138 RC632_RXCTRL1_SUBCP_8));
1142 ret = rc632_reg_write(handle, RC632_REG_DECODER_CONTROL,
1143 (RC632_DECCTRL_BPSK |
1144 RC632_DECCTRL_RXFR_14443B));
1148 ret = rc632_reg_write(handle, RC632_REG_BIT_PHASE,
1149 CM5121_14443B_BITPHASE);
1153 ret = rc632_reg_write(handle, RC632_REG_RX_THRESHOLD,
1154 CM5121_14443B_THRESHOLD);
1158 ret = rc632_reg_write(handle, RC632_REG_BPSK_DEM_CONTROL,
1159 ((0x2 & RC632_BPSKD_TAUB_MASK)<<RC632_BPSKD_TAUB_SHIFT |
1160 (0x3 & RC632_BPSKD_TAUD_MASK)<<RC632_BPSKD_TAUD_SHIFT |
1161 RC632_BPSKD_FILTER_AMP_DETECT |
1162 RC632_BPSKD_NO_RX_EOF |
1163 RC632_BPSKD_NO_RX_EGT));
1167 ret = rc632_reg_write(handle, RC632_REG_RX_CONTROL2,
1168 (RC632_RXCTRL2_AUTO_PD |
1169 RC632_RXCTRL2_DECSRC_INT));
1173 ret = rc632_reg_write(handle, RC632_REG_RX_WAIT, 0x03);
1177 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1178 (RC632_CR_TX_CRC_ENABLE |
1179 RC632_CR_RX_CRC_ENABLE |
1184 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_LSB, 0xff);
1188 ret = rc632_reg_write(handle, RC632_REG_CRC_PRESET_MSB, 0xff);
1196 rc632_iso15693_init(struct rfid_asic_handle *h)
1200 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1201 (RC632_TXCTRL_MOD_SRC_INT |
1202 RC632_TXCTRL_TX2_INV |
1203 RC632_TXCTRL_TX2_RF_EN |
1204 RC632_TXCTRL_TX1_RF_EN));
1208 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1212 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x03);
1216 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL,
1217 (RC632_CDRCTRL_RATE_15693 |
1222 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1226 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1230 ret = rc632_reg_write(h, RC632_REG_TYPE_B_FRAMING, 0x00);
1234 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1,
1235 (RC632_RXCTRL1_SUBCP_16 |
1236 RC632_RXCTRL1_ISO15693 |
1237 RC632_RXCTRL1_GAIN_35DB));
1241 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL,
1242 (RC632_DECCTRL_RXFR_15693 |
1243 RC632_DECCTRL_RX_INVERT));
1247 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0xe0);
1251 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0xff);
1255 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1259 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1260 (RC632_RXCTRL2_AUTO_PD |
1261 RC632_RXCTRL2_DECSRC_INT));
1265 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1267 RC632_CR_RX_CRC_ENABLE |
1268 RC632_CR_TX_CRC_ENABLE));
1272 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0xff);
1276 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xff);
1284 rc632_iso15693_icode_init(struct rfid_asic_handle *h)
1288 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1289 (RC632_TXCTRL_MOD_SRC_INT |
1290 RC632_TXCTRL_TX2_INV |
1291 RC632_TXCTRL_TX2_RF_EN |
1292 RC632_TXCTRL_TX1_RF_EN));
1296 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1300 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x02);
1304 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL, 0x2c);
1308 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1312 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1316 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1320 ret = rc632_reg_write(h, RC632_REG_TYPE_B_FRAMING, 0x00);
1324 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1, 0x8b); /* FIXME */
1328 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL, 0x00);
1332 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0x52);
1336 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0x66);
1340 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1344 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1345 RC632_RXCTRL2_DECSRC_INT);
1349 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1350 (RC632_CR_RX_CRC_ENABLE |
1351 RC632_CR_TX_CRC_ENABLE));
1352 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0xfe);
1356 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xff);
1364 rc632_iso15693_icl_init(struct rfid_asic_handle *h)
1370 ret = rc632_reg_write(h, RC632_REG_TX_CONTROL,
1371 (RC632_TXCTRL_MOD_SRC_INT |
1372 RC632_TXCTRL_TX2_INV |
1373 RC632_TXCTRL_TX2_RF_EN |
1374 RC632_TXCTRL_TX1_RF_EN));
1378 ret = rc632_reg_write(h, RC632_REG_CW_CONDUCTANCE, 0x3f);
1382 ret = rc632_reg_write(h, RC632_REG_MOD_CONDUCTANCE, 0x11);
1386 ret = rc632_reg_write(h, RC632_REG_CODER_CONTROL,
1387 (RC632_CDRCTRL_RATE_15693 |
1388 RC632_CDRCTRL_TXCD_ICODE_STD |
1393 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH, 0x3f);
1397 ret = rc632_reg_write(h, RC632_REG_MOD_WIDTH_SOF, 0x3f);
1400 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL1,
1401 (RC632_RXCTRL1_SUBCP_16|
1402 RC632_RXCTRL1_ISO15693|
1403 RC632_RXCTRL1_GAIN_35DB));
1406 ret = rc632_reg_write(h, RC632_REG_DECODER_CONTROL,
1407 (RC632_DECCTRL_RX_INVERT|
1408 RC632_DECCTRL_RXFR_15693));
1412 ret = rc632_reg_write(h, RC632_REG_BIT_PHASE, 0xbd);
1416 ret = rc632_reg_write(h, RC632_REG_RX_THRESHOLD, 0xff);
1420 ret = rc632_reg_write(h, RC632_REG_BPSK_DEM_CONTROL, 0x00);
1424 ret = rc632_reg_write(h, RC632_REG_RX_CONTROL2,
1425 RC632_RXCTRL2_DECSRC_INT);
1429 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY, 0x00);
1433 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_LSB, 0x12);
1437 ret = rc632_reg_write(h, RC632_REG_CRC_PRESET_MSB, 0xe0);
1444 struct mifare_authcmd {
1446 u_int8_t block_address;
1447 u_int32_t serno; /* lsb 1 2 msb */
1448 } __attribute__ ((packed));
1451 #define RFID_MIFARE_KEY_LEN 6
1452 #define RFID_MIFARE_KEY_CODED_LEN 12
1454 /* Transform crypto1 key from generic 6byte into rc632 specific 12byte */
1456 rc632_mifare_transform_key(const u_int8_t *key6, u_int8_t *key12)
1462 for (i = 0; i < RFID_MIFARE_KEY_LEN; i++) {
1463 ln = key6[i] & 0x0f;
1465 key12[i * 2 + 1] = (~ln << 4) | ln;
1466 key12[i * 2] = (~hn << 4) | hn;
1472 rc632_mifare_set_key(struct rfid_asic_handle *h, const u_int8_t *key)
1474 u_int8_t coded_key[RFID_MIFARE_KEY_CODED_LEN];
1478 ret = rc632_mifare_transform_key(key, coded_key);
1482 /* Terminate probably running command */
1483 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_IDLE);
1487 ret = rc632_fifo_write(h, RFID_MIFARE_KEY_CODED_LEN, coded_key, 0x03);
1491 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_LOAD_KEY);
1495 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1499 ret = rc632_reg_read(h, RC632_REG_ERROR_FLAG, ®);
1503 if (reg & RC632_ERR_FLAG_KEY_ERR)
1510 rc632_mifare_auth(struct rfid_asic_handle *h, u_int8_t cmd, u_int32_t serno,
1514 struct mifare_authcmd acmd;
1517 if (cmd != RFID_CMD_MIFARE_AUTH1A && cmd != RFID_CMD_MIFARE_AUTH1B) {
1518 DEBUGP("invalid auth command\n");
1522 /* Initialize acmd */
1523 acmd.block_address = block & 0xff;
1524 acmd.auth_cmd = cmd;
1525 //acmd.serno = htonl(serno);
1530 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
1531 RC632_CR_RX_CRC_ENABLE);
1533 /* Clear Rx CRC, Set Tx CRC and Odd Parity */
1534 ret = rc632_reg_write(h, RC632_REG_CHANNEL_REDUNDANCY,
1535 RC632_CR_TX_CRC_ENABLE | RC632_CR_PARITY_ODD |
1536 RC632_CR_PARITY_ENABLE);
1541 /* Send Authent1 Command */
1542 ret = rc632_fifo_write(h, sizeof(acmd), (unsigned char *)&acmd, 0x03);
1546 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT1);
1548 DEBUGP("error during AUTHENT1");
1552 /* Wait until transmitter is idle */
1553 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1557 ret = rc632_reg_read(h, RC632_REG_SECONDARY_STATUS, ®);
1561 DEBUGP("bitframe?");
1566 ret = rc632_clear_bits(h, RC632_REG_CHANNEL_REDUNDANCY,
1567 RC632_CR_TX_CRC_ENABLE);
1571 /* Send Authent2 Command */
1572 ret = rc632_reg_write(h, RC632_REG_COMMAND, RC632_CMD_AUTHENT2);
1576 /* Wait until transmitter is idle */
1577 ret = rc632_wait_idle(h, RC632_TMO_AUTH1);
1581 /* Check whether authentication was successful */
1582 ret = rc632_reg_read(h, RC632_REG_CONTROL, ®);
1586 if (!(reg & RC632_CONTROL_CRYPTO1_ON)) {
1587 DEBUGP("authentication not successful");
1594 /* transceive regular frame */
1596 rc632_mifare_transceive(struct rfid_asic_handle *handle,
1597 const u_int8_t *tx_buf, unsigned int tx_len,
1598 u_int8_t *rx_buf, unsigned int *rx_len,
1599 u_int64_t timeout, unsigned int flags)
1602 u_int8_t rxl = *rx_len & 0xff;
1604 DEBUGP("entered\n");
1605 memset(rx_buf, 0, *rx_len);
1608 ret = rc632_reg_write(handle, RC632_REG_CHANNEL_REDUNDANCY,
1609 (RC632_CR_PARITY_ENABLE |
1610 RC632_CR_PARITY_ODD |
1611 RC632_CR_TX_CRC_ENABLE |
1612 RC632_CR_RX_CRC_ENABLE));
1614 ret = rc632_clear_bits(handle, RC632_REG_CHANNEL_REDUNDANCY,
1615 RC632_CR_RX_CRC_ENABLE|RC632_CR_TX_CRC_ENABLE);
1620 ret = rc632_transceive(handle, tx_buf, tx_len, rx_buf, &rxl, 0x32, 0);
1629 const struct rfid_asic rc632 = {
1630 .name = "Philips CL RC632",
1631 .fc = ISO14443_FREQ_CARRIER,
1634 .power_up = &rc632_power_up,
1635 .power_down = &rc632_power_down,
1636 .rf_power = &rc632_rf_power,
1637 .transceive = &rc632_iso14443ab_transceive,
1639 .init = &rc632_iso14443a_init,
1640 .transceive_sf = &rc632_iso14443a_transceive_sf,
1641 .transceive_acf = &rc632_iso14443a_transceive_acf,
1642 .set_speed = &rc632_iso14443a_set_speed,
1645 .init = &rc632_iso14443b_init,
1648 .init = &rc632_iso15693_init,
1651 .setkey = &rc632_mifare_set_key,
1652 .auth = &rc632_mifare_auth,