git.rot13.org Git - BML_sump2/blob - sump2/impl/impl_sbt.project

   1 [Project]\r
   2 ProjectVersion=2.0\r
   3 Version=Lattice Semiconductor Corporation iCEcube - Release: 2015.04.27409 - Build Date: May 27 2015 16:18:59\r
   4 ProjectName=impl\r
   5 Vendor=SiliconBlue\r
   6 Synthesis=synplify\r
   7 ProjectVFiles=../source/top.v=work,../source/core.v=work,../source/mesa2ctrl.v=work,../source/mesa2lb.v=work,../source/mesa_core.v=work,../source/mesa_decode.v=work,../source/spi_byte2bit.v=work,../source/spi_prom.v=work,../source/time_stamp.v=work,../source/mesa_phy.v=work,../source/mesa_uart.v=work,../source/mesa_tx_uart.v=work,../source/mesa_ascii2nibble.v=work,../source/mesa_byte2ascii.v=work,../source/sump2.v=work,../source/top_pll.v=work\r
   8 ProjectCFiles=../constraint/top.sdc\r
   9 CurImplementation=impl_Implmnt\r
  10 Implementations=impl_Implmnt\r
  11 StartFromSynthesis=yes\r
  12 IPGeneration=false\r
  13 \r
  14 [impl_Implmnt]\r
  15 DeviceFamily=iCE40\r
  16 Device=HX1K\r
  17 DevicePackage=TQ144\r
  18 DevicePower=\r
  19 NetlistFile=impl_Implmnt/impl.edf\r
  20 AdditionalEDIFFile=\r
  21 IPEDIFFile=\r
  22 DesignLib=impl_Implmnt/sbt/netlist/oadb-top\r
  23 DesignView=_rt\r
  24 DesignCell=top\r
  25 SynthesisSDCFile=impl_Implmnt/impl.scf\r
  26 UserPinConstraintFile=\r
  27 UserSDCFile=\r
  28 PhysicalConstraintFile=../constraint/top.pcf\r
  29 BackendImplPathName=\r
  30 Devicevoltage=1.14\r
  31 DevicevoltagePerformance=+/-5%(datasheet default)\r
  32 DeviceTemperature=85\r
  33 TimingAnalysisBasedOn=Worst\r
  34 OperationRange=Commercial\r
  35 TypicalCustomTemperature=25\r
  36 WorstCustomTemperature=85\r
  37 BestCustomTemperature=0\r
  38 IOBankVoltages=topBank,2.5 bottomBank,2.5 leftBank,2.5 rightBank,2.5\r
  39 derValue=0.701346\r
  40 TimingPathNumberStick=0\r
  41 \r
  42 [lse options]\r
  43 CarryChain=True\r
  44 CarryChainLength=0\r
  45 CommandLineOptions=\r
  46 EBRUtilization=100.00\r
  47 FSMEncodingStyle=Auto\r
  48 FixGatedClocks=True\r
  49 I/OInsertion=True\r
  50 IntermediateFileDump=False\r
  51 MaximalFanout=10000\r
  52 MemoryInitialValueFileSearchPath=\r
  53 NumberOfCriticalPaths=3\r
  54 OptimizationGoal=Area\r
  55 PropagateConstants=True\r
  56 RAMStyle=Auto\r
  57 ROMStyle=Auto\r
  58 RWCheckOnRam=False\r
  59 RemoveDuplicateRegisters=True\r
  60 ResolvedMixedDrivers=False\r
  61 ResourceSharing=True\r
  62 TargetFrequency=200\r
  63 TopLevelUnit=\r
  64 UseIORegister=Auto\r
  65 VHDL2008=False\r
  66 VerilogIncludeSearchPath=\r
  67 \r
  68 [tool options]\r
  69 PlacerEffortLevel=std\r
  70 PlacerAutoLutCascade=yes\r
  71 PlacerAutoRamCascade=yes\r
  72 PlacerPowerDriven=no\r
  73 RouteWithTimingDriven=yes\r
  74 RouteWithPinPermutation=yes\r
  75 BitmapSPIFlashMode=yes\r
  76 BitmapRAM4KInit=yes\r
  77 BitmapInitRamBank=1111\r
  78 BitmapOscillatorFR=low\r
  79 BitmapEnableWarmBoot=yes\r
  80 BitmapDisableHeader=no\r
  81 BitmapSetSecurity=no\r
  82 BitmapSetNoUsedIONoPullup=no\r
  83 FloorPlannerShowFanInNets=yes\r
  84 FloorPlannerShowFanOutNets=yes\r
  85 HookTo3rdPartyTextEditor=no\r
  86 \r