2 #-- Project file C:\Users\shchen\Documents\shao\iCE_demo\to_ted\release\LED_rotation\impl\impl_syn.prj
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5 add_file -verilog -lib work "../source/top.v"
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6 add_file -verilog -lib work "../source/core.v"
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7 add_file -verilog -lib work "../source/mesa2ctrl.v"
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8 add_file -verilog -lib work "../source/mesa2lb.v"
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9 add_file -verilog -lib work "../source/mesa_core.v"
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10 add_file -verilog -lib work "../source/mesa_decode.v"
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11 add_file -verilog -lib work "../source/spi_byte2bit.v"
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12 add_file -verilog -lib work "../source/spi_prom.v"
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13 add_file -verilog -lib work "../source/time_stamp.v"
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14 add_file -verilog -lib work "../source/mesa_phy.v"
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15 add_file -verilog -lib work "../source/mesa_uart.v"
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16 add_file -verilog -lib work "../source/mesa_tx_uart.v"
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17 add_file -verilog -lib work "../source/mesa_ascii2nibble.v"
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18 add_file -verilog -lib work "../source/mesa_byte2ascii.v"
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19 add_file -verilog -lib work "../source/sump2.v"
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20 add_file -verilog -lib work "../source/top_pll.v"
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21 add_file -constraint -lib work "../constraint/top.sdc"
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22 #implementation: "impl_Implmnt"
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23 impl -add impl_Implmnt -type fpga
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25 #implementation attributes
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26 set_option -vlog_std v2001
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27 set_option -project_relative_includes 1
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30 set_option -technology SBTiCE40
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31 set_option -part iCE40HX1K
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32 set_option -package TQ144
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33 set_option -speed_grade
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34 set_option -part_companion ""
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36 #compilation/mapping options
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39 set_option -frequency auto
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40 set_option -write_verilog 0
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41 set_option -write_vhdl 0
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43 # Silicon Blue iCE40
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44 set_option -maxfan 10000
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45 set_option -disable_io_insertion 0
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47 set_option -retiming 0
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48 set_option -update_models_cp 0
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49 set_option -fixgatedclocks 2
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50 set_option -fixgeneratedclocks 0
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53 set_option -popfeed 0
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54 set_option -constprop 0
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55 set_option -createhierarchy 0
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57 # sequential_optimization_options
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58 set_option -symbolic_fsm_compiler 1
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61 set_option -compiler_compatible 0
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62 set_option -resource_sharing 1
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64 #automatic place and route (vendor) options
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65 set_option -write_apr_constraint 1
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67 #set result format/file last
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68 project -result_format "edif"
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69 project -result_file ./impl_Implmnt/impl.edf
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70 impl -active impl_Implmnt
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71 project -run synthesis -clean
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