1 /* ****************************************************************************
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2 -- (C) Copyright 2015 Kevin M. Hubbard @ Black Mesa Labs
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3 -- Source file: mesa2ctrl.v
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4 -- Date: October 4, 2015
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6 -- Language: Verilog-2001
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7 -- Description: The Mesa Bus to Control Bus translator. Decodes all subslot
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8 -- command nibbles for this slot. Write Only Operations.
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9 -- License: This project is licensed with the CERN Open Hardware Licence
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10 -- v1.2. You may redistribute and modify this project under the
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11 -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
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12 -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
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13 -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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14 -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
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15 -- v.1.2 for applicable Conditions.
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17 -- "\n"..."FFFF"."(F0-12-34-04)[11223344]\n" :
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18 -- 0xFF = Bus Idle ( NULLs )
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19 -- B0 0xF0 = New Bus Cycle to begin ( Nibble and bit orientation )
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20 -- B1 0x12 = Slot Number, 0xFF = Broadcast all slots, 0xFE = NULL Dest
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21 -- B2 0x3 = Sub-Slot within the chip (0-0xF)
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22 -- 0x4 = Command Nibble for Sub-Slot
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23 -- B3 0x04 = Number of Payload Bytes (0-255)
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24 -- 0x11223344 = Payload
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26 -- Slot 0xFF = Broadcast all slots
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27 -- Sub-Slot 0x0 = User Local Bus Access
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28 -- Sub-Slot 0xE = PROM Local Bus Access
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31 -- 0x2 = Bus Write Repeat ( burst to single address )
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32 -- 0x3 = Bus Read Repeat ( burst read from single address )
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33 -- Sub-Slot 0xF = Power and Pin Control ( Write Only )
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35 -- Revision History:
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36 -- Ver# When Who What
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37 -- ---- -------- -------- ---------------------------------------------------
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38 -- 0.1 10.04.15 khubbard Creation
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39 -- ***************************************************************************/
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40 `default_nettype none // Strictly enforce all nets to be declared
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46 input wire rx_byte_start,
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47 input wire rx_byte_stop,
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48 input wire rx_byte_rdy,
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49 input wire [7:0] rx_byte_d,
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50 output reg [8:0] subslot_ctrl
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51 ); // module mesa2ctrl
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54 reg [31:0] dword_sr;
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58 reg rx_byte_stop_p1;
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59 reg rx_byte_stop_p2;
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60 reg rx_byte_stop_p3;
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63 //-----------------------------------------------------------------------------
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64 // Shift a nibble into a byte shift register.
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65 // |---- Header ----|--- Payload ---|
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67 // Write : <F0><00><00><08>[<ADDR><DATA>]
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68 // Read : <F0><00><00><08>[<ADDR><Length>]
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69 //-----------------------------------------------------------------------------
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70 always @ ( posedge clk ) begin : proc_lb1
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71 rx_byte_rdy_p1 <= rx_byte_rdy;
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72 rx_byte_rdy_p2 <= rx_byte_rdy_p1;
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73 rx_byte_rdy_p3 <= rx_byte_rdy_p2;
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74 rx_byte_stop_p1 <= rx_byte_stop;
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75 rx_byte_stop_p2 <= rx_byte_stop_p1;
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76 rx_byte_stop_p3 <= rx_byte_stop_p2;
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78 if ( rx_byte_start == 1 ) begin
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80 end else if ( rx_byte_rdy == 1 ) begin
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81 if ( byte_cnt != 4'd4 ) begin
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82 byte_cnt <= byte_cnt + 1;
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86 // Shift bytes into a 32bit SR
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87 if ( rx_byte_rdy == 1 ) begin
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88 dword_sr[31:0] <= { dword_sr[23:0], rx_byte_d[7:0] };
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91 subslot_ctrl[8] <= 0;// Strobe
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92 // Accept single DWORD packets for Slot-00 (this) or Slot-FF (all)
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93 if ( rx_byte_rdy_p2 == 1 && byte_cnt[3:0] == 4'd3 ) begin
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94 if ( dword_sr[31:16] == 16'hF000 ||
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95 dword_sr[31:16] == 16'hF0FF ) begin
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96 // Payload must be 0x00 length
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97 if ( dword_sr[7:0] == 8'h00 ) begin
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98 subslot_ctrl <= { 1'b1, dword_sr[15:8] };// D(8) is Strobe
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103 if ( reset == 1 ) begin
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110 endmodule // mesa2ctrl
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