1 /* ****************************************************************************
\r
2 -- Source file: mesa_ascii2nibble.v
\r
3 -- Date: October 4, 2015
\r
5 -- Description: Convert an ASCII character to a binary nibble.
\r
6 -- Language: Verilog-2001 and VHDL-1993
\r
7 -- Simulation: Mentor-Modelsim
\r
8 -- Synthesis: Lattice
\r
9 -- License: This project is licensed with the CERN Open Hardware Licence
\r
10 -- v1.2. You may redistribute and modify this project under the
\r
11 -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
\r
12 -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
\r
13 -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
\r
14 -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
\r
15 -- v.1.2 for applicable Conditions.
\r
17 -- Revision History:
\r
18 -- Ver# When Who What
\r
19 -- ---- -------- -------- ---------------------------------------------------
\r
20 -- 0.1 10.04.15 khubbard Creation
\r
21 -- ***************************************************************************/
\r
22 `default_nettype none // Strictly enforce all nets to be declared
\r
24 module mesa_ascii2nibble
\r
27 input wire rx_char_en,
\r
28 input wire [7:0] rx_char_d,
\r
29 output reg rx_nib_en,
\r
30 output reg [3:0] rx_nib_d
\r
31 );// module mesa_ascii2nibble
\r
33 reg [4:0] rx_nib_bin; // MSB is Valid Char Flag for "0"-"F"
\r
36 //-----------------------------------------------------------------------------
\r
37 // When UART receives an ASCII char, see if it is 0-9,a-f,A-F else toss
\r
38 //-----------------------------------------------------------------------------
\r
39 always @ ( posedge clk ) begin : proc_rx
\r
40 rx_nib_d <= rx_nib_bin[3:0];
\r
41 rx_nib_en <= rx_char_en & rx_nib_bin[4];
\r
45 //-----------------------------------------------------------------------------
\r
46 // Convert ASCII to binary nibbles. Toss and ignore all other received chars
\r
53 //-----------------------------------------------------------------------------
\r
54 always @ ( * ) begin : proc_lut
\r
56 case( rx_char_d[7:0] )
\r
57 8'h30 : rx_nib_bin[4:0] <= 5'h10;// 0
\r
58 8'h31 : rx_nib_bin[4:0] <= 5'h11;
\r
59 8'h32 : rx_nib_bin[4:0] <= 5'h12;
\r
60 8'h33 : rx_nib_bin[4:0] <= 5'h13;
\r
61 8'h34 : rx_nib_bin[4:0] <= 5'h14;
\r
62 8'h35 : rx_nib_bin[4:0] <= 5'h15;
\r
63 8'h36 : rx_nib_bin[4:0] <= 5'h16;
\r
64 8'h37 : rx_nib_bin[4:0] <= 5'h17;
\r
65 8'h38 : rx_nib_bin[4:0] <= 5'h18;
\r
66 8'h39 : rx_nib_bin[4:0] <= 5'h19;// 9
\r
68 8'h41 : rx_nib_bin[4:0] <= 5'h1A;// A
\r
69 8'h42 : rx_nib_bin[4:0] <= 5'h1B;
\r
70 8'h43 : rx_nib_bin[4:0] <= 5'h1C;
\r
71 8'h44 : rx_nib_bin[4:0] <= 5'h1D;
\r
72 8'h45 : rx_nib_bin[4:0] <= 5'h1E;
\r
73 8'h46 : rx_nib_bin[4:0] <= 5'h1F;// F
\r
75 8'h61 : rx_nib_bin[4:0] <= 5'h1A;// a
\r
76 8'h62 : rx_nib_bin[4:0] <= 5'h1B;
\r
77 8'h63 : rx_nib_bin[4:0] <= 5'h1C;
\r
78 8'h64 : rx_nib_bin[4:0] <= 5'h1D;
\r
79 8'h65 : rx_nib_bin[4:0] <= 5'h1E;
\r
80 8'h66 : rx_nib_bin[4:0] <= 5'h1F;// f
\r
82 default : rx_nib_bin[4:0] <= 5'h0F;
\r
88 endmodule // mesa_ascii2nibble
\r