1 /* ****************************************************************************
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2 -- (C) Copyright 2015 Black Mesa Labs
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3 -- Source file: mesa_tx_uart.v
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4 -- Date: June 1, 2015
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6 -- Description: TX only 1/2 of UART for transmitting Wo bytes.
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7 -- Language: Verilog-2001
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8 -- License: This project is licensed with the CERN Open Hardware Licence
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9 -- v1.2. You may redistribute and modify this project under the
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10 -- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
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11 -- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
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12 -- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
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13 -- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
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14 -- v.1.2 for applicable Conditions.
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16 -- RXD \START/<D0><D1><D2><..><D7>/STOP
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17 -- Design Statistics after Packing
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19 -- Number of LUTs : 190 / 384
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20 -- Number of DFFs : 110 / 384
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22 -- Revision History:
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23 -- Ver# When Who What
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24 -- ---- -------- -------- ---------------------------------------------------
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25 -- 0.1 06.01.15 khubbard Creation
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26 -- ***************************************************************************/
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27 //`default_nettype none // Strictly enforce all nets to be declared
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33 input wire [7:0] tx_byte,
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37 input wire baud_lock,
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38 input wire [15:0] baud_rate
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39 ); // module mesa_tx_uart
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42 reg [15:0] tx_cnt_16b;
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43 reg [3:0] tx_bit_cnt;
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53 //-----------------------------------------------------------------------------
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54 // TX : Load 8bits into 10bit SR and shift out at the RX baud rate
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55 //-----------------------------------------------------------------------------
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56 always @ ( posedge clk ) begin : proc_tx
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61 txd_loc <= tx_sr[0];
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64 baud_lock_p1 <= baud_lock;
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65 send_lf <= baud_lock & ~ baud_lock_p1;
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67 // Load a new Byte to send
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68 if ( ( tx_en == 1 && tx_en_p1 == 0 ) || ( send_lf == 1 ) ) begin
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69 tx_bit_cnt <= 4'd10;
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70 tx_cnt_16b <= 16'h0000;
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73 tx_sr[9:0] <= { 1'b1, tx_byte[7:0], 1'b0 };
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74 if ( send_lf == 1 ) begin
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75 tx_sr[9:0] <= { 1'b1, 8'h0A , 1'b0 };// Used for autobauding next node
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78 // Shift and send the byte until bit_cnt goes to 0
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79 end else if ( tx_bit_cnt != 4'd0 ) begin
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80 tx_cnt_16b <= tx_cnt_16b + 1;
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82 if ( tx_now == 1 ) begin
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84 tx_bit_cnt <= tx_bit_cnt[3:0] - 1;
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85 tx_cnt_16b <= 16'h0000;
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86 tx_sr[9:0] <= { 1'b1, tx_sr[9:1] };
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92 if ( tx_cnt_16b[15:0] == baud_rate[15:0] ) begin
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96 if ( reset == 1 ) begin
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104 endmodule // mesa_tx_uart
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