1 module top_pll(REFERENCECLK,
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8 input RESET; /* To initialize the simulation properly, the RESET signal (Active Low) must be asserted at the beginning of the simulation */
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10 output PLLOUTGLOBAL;
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13 SB_PLL40_CORE top_pll_inst(.REFERENCECLK(REFERENCECLK),
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14 .PLLOUTCORE(PLLOUTCORE),
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15 .PLLOUTGLOBAL(PLLOUTGLOBAL),
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26 //\\ Fin=12, Fout=96;
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27 defparam top_pll_inst.DIVR = 4'b0000;
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28 defparam top_pll_inst.DIVF = 7'b0111111;
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29 defparam top_pll_inst.DIVQ = 3'b011;
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30 defparam top_pll_inst.FILTER_RANGE = 3'b001;
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31 defparam top_pll_inst.FEEDBACK_PATH = "SIMPLE";
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32 defparam top_pll_inst.DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED";
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33 defparam top_pll_inst.FDA_FEEDBACK = 4'b0000;
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34 defparam top_pll_inst.DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED";
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35 defparam top_pll_inst.FDA_RELATIVE = 4'b0000;
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36 defparam top_pll_inst.SHIFTREG_DIV_MODE = 2'b00;
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37 defparam top_pll_inst.PLLOUT_SELECT = "GENCLK";
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38 defparam top_pll_inst.ENABLE_ICEGATE = 1'b0;
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