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Merge master.kernel.org:/home/rmk/linux-2.6-arm
[powerpc.git]
/
arch
/
arm
/
kernel
/
entry-armv.S
diff --git
a/arch/arm/kernel/entry-armv.S
b/arch/arm/kernel/entry-armv.S
index
de4e331
..
d645897
100644
(file)
--- a/
arch/arm/kernel/entry-armv.S
+++ b/
arch/arm/kernel/entry-armv.S
@@
-27,6
+27,7
@@
* Interrupt handling. Preserves r7, r8, r9
*/
.macro irq_handler
* Interrupt handling. Preserves r7, r8, r9
*/
.macro irq_handler
+ get_irqnr_preamble r5, lr
1: get_irqnr_and_base r0, r6, r5, lr
movne r1, sp
@
1: get_irqnr_and_base r0, r6, r5, lr
movne r1, sp
@
@@
-99,7
+100,6
@@
common_invalid:
@ cpsr_<exception>, "old_r0"
mov r0, sp
@ cpsr_<exception>, "old_r0"
mov r0, sp
- and r2, r6, #0x1f
b bad_mode
/*
b bad_mode
/*
@@
-191,6
+191,9
@@
__dabt_svc:
__irq_svc:
svc_entry
__irq_svc:
svc_entry
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_off
+#endif
#ifdef CONFIG_PREEMPT
get_thread_info tsk
ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
#ifdef CONFIG_PREEMPT
get_thread_info tsk
ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
@@
-211,6
+214,10
@@
preempt_return:
#endif
ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr_cxsf, r0
#endif
ldr r0, [sp, #S_PSR] @ irqs are already disabled
msr spsr_cxsf, r0
+#ifdef CONFIG_TRACE_IRQFLAGS
+ tst r0, #PSR_I_BIT
+ bleq trace_hardirqs_on
+#endif
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.ltorg
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.ltorg
@@
-398,6
+405,9
@@
__dabt_usr:
__irq_usr:
usr_entry
__irq_usr:
usr_entry
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_off
+#endif
get_thread_info tsk
#ifdef CONFIG_PREEMPT
ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
get_thread_info tsk
#ifdef CONFIG_PREEMPT
ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
@@
-412,6
+422,9
@@
__irq_usr:
teq r0, r7
strne r0, [r0, -r0]
#endif
teq r0, r7
strne r0, [r0, -r0]
#endif
+#ifdef CONFIG_TRACE_IRQFLAGS
+ bl trace_hardirqs_on
+#endif
mov why, #0
b ret_to_user
mov why, #0
b ret_to_user
@@
-423,7
+436,7
@@
__und_usr:
usr_entry
tst r3, #PSR_T_BIT @ Thumb mode?
usr_entry
tst r3, #PSR_T_BIT @ Thumb mode?
- bne
fpundefinstr
@ ignore FP
+ bne
__und_usr_unknown
@ ignore FP
sub r4, r2, #4
@
sub r4, r2, #4
@
@@
-435,7
+448,7
@@
__und_usr:
@
1: ldrt r0, [r4]
adr r9, ret_from_exception
@
1: ldrt r0, [r4]
adr r9, ret_from_exception
- adr lr,
fpundefinstr
+ adr lr,
__und_usr_unknown
@
@ fallthrough to call_fpe
@
@
@ fallthrough to call_fpe
@
@@
-463,7
+476,9
@@
__und_usr:
* Emulators may wish to make use of the following registers:
* r0 = instruction opcode.
* r2 = PC+4
* Emulators may wish to make use of the following registers:
* r0 = instruction opcode.
* r2 = PC+4
+ * r9 = normal "successful" return address
* r10 = this threads thread_info structure.
* r10 = this threads thread_info structure.
+ * lr = unrecognised instruction return address
*/
call_fpe:
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
*/
call_fpe:
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
@@
-532,10
+547,12
@@
do_fpe:
.data
ENTRY(fp_enter)
.data
ENTRY(fp_enter)
- .word
fpundefinstr
+ .word
no_fp
.text
.text
-fpundefinstr:
+no_fp: mov pc, lr
+
+__und_usr_unknown:
mov r0, sp
adr lr, ret_from_exception
b do_undefinstr
mov r0, sp
adr lr, ret_from_exception
b do_undefinstr
@@
-576,10
+593,6
@@
ENTRY(__switch_to)
strex r5, r4, [ip] @ Clear exclusive monitor
#endif
#endif
strex r5, r4, [ip] @ Clear exclusive monitor
#endif
#endif
-#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
- mra r4, r5, acc0
- stmia ip, {r4, r5}
-#endif
#if defined(CONFIG_HAS_TLS_REG)
mcr p15, 0, r3, c13, c0, 3 @ set TLS register
#elif !defined(CONFIG_TLS_REG_EMUL)
#if defined(CONFIG_HAS_TLS_REG)
mcr p15, 0, r3, c13, c0, 3 @ set TLS register
#elif !defined(CONFIG_TLS_REG_EMUL)
@@
-588,11
+601,6
@@
ENTRY(__switch_to)
#endif
#ifdef CONFIG_MMU
mcr p15, 0, r6, c3, c0, 0 @ Set domain register
#endif
#ifdef CONFIG_MMU
mcr p15, 0, r6, c3, c0, 0 @ Set domain register
-#endif
-#if defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_IWMMXT)
- add r4, r2, #TI_CPU_DOMAIN + 40 @ cpu_context_save->extra
- ldmib r4, {r4, r5}
- mar acc0, r4, r5
#endif
mov r5, r0
add r4, r2, #TI_CPU_SAVE
#endif
mov r5, r0
add r4, r2, #TI_CPU_SAVE