- /*
- * Receives on channel 0
- */
-
- /*
- * It's important to test all the bits (or at least the
- * EOP_SEEN bit) when deciding to do the RX process
- * particularly when coalescing, to make sure we
- * take care of the following:
- *
- * If you have some packets waiting (have been received
- * but no interrupt) and get a TX interrupt before
- * the RX timer or counter expires, reading the ISR
- * above will clear the timer and counter, and you
- * won't get another interrupt until a packet shows
- * up to start the timer again. Testing
- * EOP_SEEN here takes care of this case.
- * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
- */
-
-
- if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
- sbdma_rx_process(sc,&(sc->sbm_rxdma));
+ if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
+ if (netif_rx_schedule_prep(dev)) {
+ __raw_writeq(0, sc->sbm_imr);
+ __netif_rx_schedule(dev);
+ /* Depend on the exit from poll to reenable intr */
+ }
+ else {
+ /* may leave some packets behind */
+ sbdma_rx_process(sc,&(sc->sbm_rxdma),
+ SBMAC_MAX_RXDESCR * 2, 0);