-#define UART_PUT_CR(port,v) writel(v, (port)->membase + ATMEL_US_CR)
-#define UART_GET_MR(port) readl((port)->membase + ATMEL_US_MR)
-#define UART_PUT_MR(port,v) writel(v, (port)->membase + ATMEL_US_MR)
-#define UART_PUT_IER(port,v) writel(v, (port)->membase + ATMEL_US_IER)
-#define UART_PUT_IDR(port,v) writel(v, (port)->membase + ATMEL_US_IDR)
-#define UART_GET_IMR(port) readl((port)->membase + ATMEL_US_IMR)
-#define UART_GET_CSR(port) readl((port)->membase + ATMEL_US_CSR)
-#define UART_GET_CHAR(port) readl((port)->membase + ATMEL_US_RHR)
-#define UART_PUT_CHAR(port,v) writel(v, (port)->membase + ATMEL_US_THR)
-#define UART_GET_BRGR(port) readl((port)->membase + ATMEL_US_BRGR)
-#define UART_PUT_BRGR(port,v) writel(v, (port)->membase + ATMEL_US_BRGR)
-#define UART_PUT_RTOR(port,v) writel(v, (port)->membase + ATMEL_US_RTOR)
-
-// #define UART_GET_CR(port) readl((port)->membase + ATMEL_US_CR) // is write-only
+#define UART_PUT_CR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_CR)
+#define UART_GET_MR(port) __raw_readl((port)->membase + ATMEL_US_MR)
+#define UART_PUT_MR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_MR)
+#define UART_PUT_IER(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IER)
+#define UART_PUT_IDR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_IDR)
+#define UART_GET_IMR(port) __raw_readl((port)->membase + ATMEL_US_IMR)
+#define UART_GET_CSR(port) __raw_readl((port)->membase + ATMEL_US_CSR)
+#define UART_GET_CHAR(port) __raw_readl((port)->membase + ATMEL_US_RHR)
+#define UART_PUT_CHAR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_THR)
+#define UART_GET_BRGR(port) __raw_readl((port)->membase + ATMEL_US_BRGR)
+#define UART_PUT_BRGR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_BRGR)
+#define UART_PUT_RTOR(port,v) __raw_writel(v, (port)->membase + ATMEL_US_RTOR)
+
+// #define UART_GET_CR(port) __raw_readl((port)->membase + ATMEL_US_CR) // is write-only