+ jtag430_haltcpu();
+
+ //FCTL1=0xA540, enabling flash write
+ jtag430_writemem(0x0128, 0xA540);
+ //FCTL2=0xA540, selecting MCLK as source, DIV=1
+ jtag430_writemem(0x012A, 0xA540);
+ //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
+ jtag430_writemem(0x012C, 0xA500); //all but info flash.
+ //if(jtag430_readmem(0x012C));
+
+ //Write the word itself.
+ jtag430_writeflashword(adr,data);
+
+ //FCTL1=0xA500, disabling flash write
+ jtag430_writemem(0x0128, 0xA500);
+
+ //jtag430_releasecpu();
+}
+
+
+
+//! Power-On Reset
+void jtag430_por(){
+ // Perform Reset
+ jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift_16(0x2C01); // apply
+ jtag_dr_shift_16(0x2401); // remove
+ CLRTCLK;
+ SETTCLK;
+ CLRTCLK;
+ SETTCLK;
+ CLRTCLK;
+ jtagid = jtag_ir_shift_8(IR_ADDR_CAPTURE); // get JTAG identifier
+ SETTCLK;
+
+ jtag430_writemem(0x0120, 0x5A80); // Diabled Watchdog
+}
+
+
+
+#define ERASE_GLOB 0xA50E
+#define ERASE_ALLMAIN 0xA50C
+#define ERASE_MASS 0xA506
+#define ERASE_MAIN 0xA504
+#define ERASE_SGMT 0xA502
+
+//! Configure flash, then write a word.
+void jtag430_eraseflash(unsigned int mode, unsigned int adr, unsigned int count,
+ unsigned int info){
+ jtag430_haltcpu();
+
+ //FCTL1= erase mode
+ jtag430_writemem(0x0128, mode);
+ //FCTL2=0xA540, selecting MCLK as source, DIV=1
+ jtag430_writemem(0x012A, 0xA540);
+ //FCTL3=0xA500, should be 0xA540 for Info Seg A on 2xx chips.
+ if(info)
+ jtag430_writemem(0x012C, 0xA540);
+ else
+ jtag430_writemem(0x012C, 0xA500);
+
+ //Write the erase word.
+ jtag430_writemem(adr, 0x55AA);
+ //Return to read mode.
+ CLRTCLK;
+ jtag_ir_shift_8(IR_CNTRL_SIG_16BIT);
+ jtag_dr_shift_16(0x2409);
+
+ //Send the pulses.
+ jtag430_tclk_flashpulses(count);
+
+ //FCTL1=0xA500, disabling flash write
+ jtag430_writemem(0x0128, 0xA500);
+
+ //jtag430_releasecpu();