+
+
+
+
+/*****************************
+Captured from FlySwatter against AT91SAM7S, to be used by me for testing. ignore
+
+> arm reg
+System and User mode registers
+ r0: 300000df r1: 00000000 r2: 58000000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 000000fc
+ cpsr: 00000093
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000000 spsr_abt: e00000ff
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+>
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Supervisor
+cpsr: 0x00000093 pc: 0x00000100
+System and User mode registers
+ r0: 300000df r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000100
+ cpsr: 00000093
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000000 spsr_abt: e00000ff
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+>
+ step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+> step;arm reg
+target state: halted
+target halted in ARM state due to single-step, current mode: Abort
+cpsr: 0x00000097 pc: 0x00000010
+System and User mode registers
+ r0: 300000e3 r1: 00000000 r2: 00200000 r3: 00200a75
+ r4: fffb0000 r5: 00000002 r6: 00000000 r7: 00200f6c
+ r8: 00000000 r9: 00000000 r10: ffffffff r11: 00000000
+ r12: 00000009 sp_usr: 00000000 lr_usr: 00000000 pc: 00000010
+ cpsr: 00000097
+
+FIQ mode shadow registers
+ r8_fiq: 00000000 r9_fiq: fffcc000 r10_fiq: fffff400 r11_fiq: fffff000
+ r12_fiq: 00200f44 sp_fiq: 00000000 lr_fiq: 00000000 spsr_fiq: f00000fb
+
+Supervisor mode shadow registers
+ sp_svc: 00201f78 lr_svc: 00200a75 spsr_svc: 400000b3
+
+Abort mode shadow registers
+ sp_abt: 00000000 lr_abt: 00000108 spsr_abt: 00000093
+
+IRQ mode shadow registers
+ sp_irq: 00000000 lr_irq: 00000000 spsr_irq: f000003b
+
+Undefined instruction mode shadow registers
+ sp_und: 00000000 lr_und: 00000000 spsr_und: 300000df
+>
+*/