projects
/
goodfet
/ blobdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
raw
|
inline
| side by side
SPI Flash Erase command.
[goodfet]
/
firmware
/
lib
/
msp430f1612.c
diff --git
a/firmware/lib/msp430f1612.c
b/firmware/lib/msp430f1612.c
index
fb6c4c0
..
58797ed
100644
(file)
--- a/
firmware/lib/msp430f1612.c
+++ b/
firmware/lib/msp430f1612.c
@@
-29,20
+29,21
@@
void setbaud(unsigned char rate){
//http://mspgcc.sourceforge.net/baudrate.html
switch(rate){
//http://mspgcc.sourceforge.net/baudrate.html
switch(rate){
- default:
- case 0:
case 1://9600 baud
case 1://9600 baud
- UBR00=0x
00; UBR10=0x01; UMCTL0=0x00;
+ UBR00=0x
7F; UBR10=0x01; UMCTL0=0x5B; /* uart0 3683400Hz 9599bps */
break;
case 2://19200 baud
break;
case 2://19200 baud
- UBR00=0x
00; UBR10=0x02; UMCTL0=0x00;
+ UBR00=0x
BF; UBR10=0x00; UMCTL0=0xF7; /* uart0 3683400Hz 19194bps */
break;
case 3://38400 baud
break;
case 3://38400 baud
- UBR00=0x
40; UBR10=0x00; UMCTL0=0x00;
+ UBR00=0x
5F; UBR10=0x00; UMCTL0=0xBF; /* uart0 3683400Hz 38408bps */
break;
break;
- //TODO
case 4://57600 baud
case 4://57600 baud
+ UBR00=0x40; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 57553bps */
+ break;
+ default:
case 5://115200 baud
case 5://115200 baud
+ UBR00=0x20; UBR10=0x00; UMCTL0=0x00; /* uart0 3683400Hz 115106bps */
break;
}
}
break;
}
}
@@
-74,19
+75,39
@@
void msp430_init_uart(){
void msp430_init_dco() {
/* This code taken from the FU Berlin sources and reformatted. */
void msp430_init_dco() {
/* This code taken from the FU Berlin sources and reformatted. */
-#define MSP430_CPU_SPEED 2457600UL
+ //
+
+//Works well.
+//#define MSP430_CPU_SPEED 2457600UL
+
+//Too fast for internal resistor.
+//#define MSP430_CPU_SPEED 4915200UL
+
+//Max speed.
+//#deefine MSP430_CPU_SPEED 4500000UL
+
+//baud rate speed
+#define MSP430_CPU_SPEED 3683400UL
#define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
unsigned int compare, oldcapture = 0;
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; //stop WDT
#define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
unsigned int compare, oldcapture = 0;
unsigned int i;
WDTCTL = WDTPW + WDTHOLD; //stop WDT
+
+
+ DCOCTL=0xF0;
+ //a4
+ //1100
- BCSCTL1 = 0xa4; /* ACLK is devided by 4. RSEL=6 no division for MCLK
- and SSMCLK. XT2 is off. */
-
+ /* ACLK is devided by 4. RSEL=6 no division for MCLK
+ and SSMCLK. XT2 is off. */
+ //BCSCTL1 = 0xa8;
+
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */
-
+
+ P1OUT|=1;
+
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
asm("nop");
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
asm("nop");
@@
-119,10
+140,12
@@
void msp430_init_dco() {
/* -> Select next higher RSEL */
}
}
/* -> Select next higher RSEL */
}
}
-
+
CCTL2 = 0; /* Stop CCR2 function */
TACTL = 0; /* Stop Timer_A */
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
CCTL2 = 0; /* Stop CCR2 function */
TACTL = 0; /* Stop Timer_A */
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
+
+ P1OUT=0;
}
}