+/* This code taken from the FU Berlin sources and reformatted. */
+ //
+
+//Works well.
+//#define MSP430_CPU_SPEED 2457600UL
+
+//Too fast for internal resistor.
+//#define MSP430_CPU_SPEED 4915200UL
+
+//Max speed.
+//#define MSP430_CPU_SPEED 4500000UL
+
+//baud rate speed
+#define MSP430_CPU_SPEED 3683400UL
+#define DELTA ((MSP430_CPU_SPEED) / (32768 / 8))
+ unsigned int compare, oldcapture = 0;
+ unsigned int i;
+
+ WDTCTL = WDTPW + WDTHOLD; //stop WDT
+
+
+ DCOCTL=0xF0;
+ //a4
+ //1100
+
+ /* ACLK is devided by 4. RSEL=6 no division for MCLK
+ and SSMCLK. XT2 is off. */
+ //BCSCTL1 = 0xa8;
+
+ BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
+ crystal DCO frquenzy = 2,4576 MHz */
+
+ PLEDOUT|=PLEDPIN;
+
+ BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
+ for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
+ asm("nop");
+ }
+
+ CCTL2 = CCIS0 + CM0 + CAP; // Define CCR2, CAP, ACLK
+ TACTL = TASSEL1 + TACLR + MC1; // SMCLK, continous mode
+
+
+ while(1) {
+
+ while((CCTL2 & CCIFG) != CCIFG); /* Wait until capture occured! */
+ CCTL2 &= ~CCIFG; /* Capture occured, clear flag */
+ compare = CCR2; /* Get current captured SMCLK */
+ compare = compare - oldcapture; /* SMCLK difference */
+ oldcapture = CCR2; /* Save current captured SMCLK */
+
+ if(DELTA == compare) {
+ break; /* if equal, leave "while(1)" */
+ } else if(DELTA < compare) { /* DCO is too fast, slow it down */
+ DCOCTL--;
+ if(DCOCTL == 0xFF) { /* Did DCO role under? */
+ BCSCTL1--;
+ }
+ } else { /* -> Select next lower RSEL */
+ DCOCTL++;
+ if(DCOCTL == 0x00) { /* Did DCO role over? */
+ BCSCTL1++;
+ }
+ /* -> Select next higher RSEL */
+ }
+ }
+
+ CCTL2 = 0; /* Stop CCR2 function */
+ TACTL = 0; /* Stop Timer_A */
+
+ BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
+
+ PLEDOUT=~PLEDPIN;
+