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yay! getting there. still odd register bugs, but getting there with peek.
[goodfet]
/
firmware
/
lib
/
msp430x1612.c
diff --git
a/firmware/lib/msp430x1612.c
b/firmware/lib/msp430x1612.c
index
7d6b7c1
..
9d28415
100644
(file)
--- a/
firmware/lib/msp430x1612.c
+++ b/
firmware/lib/msp430x1612.c
@@
-204,7
+204,7
@@
void msp430_init_dco() {
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */
BCSCTL2 = 0x00; /* Init FLL to desired frequency using the 32762Hz
crystal DCO frquenzy = 2,4576 MHz */
- P
1OUT|=1
;
+ P
LEDOUT|=PLEDPIN
;
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
BCSCTL1 |= DIVA1 + DIVA0; /* ACLK = LFXT1CLK/8 */
for(i = 0xffff; i > 0; i--) { /* Delay for XTAL to settle */
@@
-244,7
+244,7
@@
void msp430_init_dco() {
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
BCSCTL1 &= ~(DIVA1 + DIVA0); /* remove /8 divisor from ACLK again */
- P
1OUT=0
;
+ P
LEDOUT=~PLEDPIN
;
}
}