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Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux...
[powerpc.git]
/
include
/
asm-mips
/
mipsregs.h
diff --git
a/include/asm-mips/mipsregs.h
b/include/asm-mips/mipsregs.h
index
706b369
..
aa17f65
100644
(file)
--- a/
include/asm-mips/mipsregs.h
+++ b/
include/asm-mips/mipsregs.h
@@
-707,10
+707,10
@@
do { \
*/
#define __read_64bit_c0_split(source, sel) \
({ \
*/
#define __read_64bit_c0_split(source, sel) \
({ \
- unsigned long long
val;
\
- unsigned long
flags;
\
+ unsigned long long
__val;
\
+ unsigned long
__flags;
\
\
\
- local_irq_save(
flags);
\
+ local_irq_save(
__flags);
\
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
@@
-719,7
+719,7
@@
do { \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
- : "=r" (
val));
\
+ : "=r" (
__val));
\
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
else \
__asm__ __volatile__( \
".set\tmips64\n\t" \
@@
-728,17
+728,17
@@
do { \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
"dsrl\t%M0, %M0, 32\n\t" \
"dsrl\t%L0, %L0, 32\n\t" \
".set\tmips0" \
- : "=r" (
val));
\
- local_irq_restore(
flags);
\
+ : "=r" (
__val));
\
+ local_irq_restore(
__flags);
\
\
\
-
val;
\
+
__val;
\
})
#define __write_64bit_c0_split(source, sel, val) \
do { \
})
#define __write_64bit_c0_split(source, sel, val) \
do { \
- unsigned long
flags;
\
+ unsigned long
__flags;
\
\
\
- local_irq_save(
flags);
\
+ local_irq_save(
__flags);
\
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
if (sel == 0) \
__asm__ __volatile__( \
".set\tmips64\n\t" \
@@
-759,7
+759,7
@@
do { \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: : "r" (val)); \
"dmtc0\t%L0, " #source ", " #sel "\n\t" \
".set\tmips0" \
: : "r" (val)); \
- local_irq_restore(
flags);
\
+ local_irq_restore(
__flags);
\
} while (0)
#define read_c0_index() __read_32bit_c0_register($0, 0)
} while (0)
#define read_c0_index() __read_32bit_c0_register($0, 0)
@@
-981,7
+981,7
@@
do { \
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
/* MIPSR2 */
#define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
/* MIPSR2 */
-#define read_c0_hwrena() __read_32bit_c0_register($7,0)
+#define read_c0_hwrena() __read_32bit_c0_register($7,
0)
#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_intctl() __read_32bit_c0_register($12, 1)
#define write_c0_hwrena(val) __write_32bit_c0_register($7, 0, val)
#define read_c0_intctl() __read_32bit_c0_register($12, 1)
@@
-993,7
+993,7
@@
do { \
#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
#define read_c0_srsmap() __read_32bit_c0_register($12, 3)
#define write_c0_srsmap(val) __write_32bit_c0_register($12, 3, val)
-#define read_c0_ebase() __read_32bit_c0_register($15,1)
+#define read_c0_ebase() __read_32bit_c0_register($15,
1)
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
/*
#define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
/*