ARM: dts: tegra30: beaver: Setup voltage regulators for DVFS

[linux] / arch / arm / boot / dts / tegra30-beaver.dts

diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts
index a3b0f35..f8252fb 100644 (file)
--- a/arch/arm/boot/dts/tegra30-beaver.dts
+++ b/arch/arm/boot/dts/tegra30-beaver.dts
@@ -1807,7 +1807,10 @@
                                vddctrl_reg: vddctrl {
                                        regulator-name = "vdd_cpu,vdd_sys";
                                        regulator-min-microvolt = <1000000>;
-                                       regulator-max-microvolt = <1000000>;
+                                       regulator-max-microvolt = <1250000>;
+                                       regulator-coupled-with = <&core_vdd_reg>;
+                                       regulator-coupled-max-spread = <300000>;
+                                       regulator-max-step-microvolt = <100000>;
                                        regulator-always-on;
                                };
 
@@ -1868,13 +1871,16 @@
                        };
                };
 
-               tps62361@60 {
+               core_vdd_reg: tps62361@60 {
                        compatible = "ti,tps62361";
                        reg = <0x60>;
 
                        regulator-name = "tps62361-vout";
                        regulator-min-microvolt = <500000>;
                        regulator-max-microvolt = <1500000>;
+                       regulator-coupled-with = <&vddctrl_reg>;
+                       regulator-coupled-max-spread = <300000>;
+                       regulator-max-step-microvolt = <100000>;
                        regulator-boot-on;
                        regulator-always-on;
                        ti,vsel0-state-high;
@@ -2114,4 +2120,11 @@
                         <&tegra_car TEGRA30_CLK_EXTERN1>;
                clock-names = "pll_a", "pll_a_out0", "mclk";
        };
+
+       cpus {
+               cpu0: cpu@0 {
+                       cpu-supply = <&vddctrl_reg>;
+                       core-supply = <&core_vdd_reg>;
+               };
+       };
 };