#include <asm/hardware.h>
#include "generic.h"
+#include "clock.h"
static struct map_desc at91rm9200_io_desc[] __initdata = {
{
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SPI,
- .pfn = __phys_to_pfn(AT91_BASE_SPI),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_SPI),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SSC2,
- .pfn = __phys_to_pfn(AT91_BASE_SSC2),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SSC1,
- .pfn = __phys_to_pfn(AT91_BASE_SSC1),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_SSC0,
- .pfn = __phys_to_pfn(AT91_BASE_SSC0),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_SSC0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US3,
- .pfn = __phys_to_pfn(AT91_BASE_US3),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_US3),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US2,
- .pfn = __phys_to_pfn(AT91_BASE_US2),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_US2),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US1,
- .pfn = __phys_to_pfn(AT91_BASE_US1),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_US1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_US0,
- .pfn = __phys_to_pfn(AT91_BASE_US0),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_US0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_EMAC,
- .pfn = __phys_to_pfn(AT91_BASE_EMAC),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_EMAC),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_TWI,
- .pfn = __phys_to_pfn(AT91_BASE_TWI),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_TWI),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_MCI,
- .pfn = __phys_to_pfn(AT91_BASE_MCI),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_MCI),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_UDP,
- .pfn = __phys_to_pfn(AT91_BASE_UDP),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_UDP),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_TCB1,
- .pfn = __phys_to_pfn(AT91_BASE_TCB1),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB1),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_VA_BASE_TCB0,
- .pfn = __phys_to_pfn(AT91_BASE_TCB0),
+ .pfn = __phys_to_pfn(AT91RM9200_BASE_TCB0),
.length = SZ_16K,
.type = MT_DEVICE,
}, {
.virtual = AT91_SRAM_VIRT_BASE,
- .pfn = __phys_to_pfn(AT91_SRAM_BASE),
- .length = AT91_SRAM_SIZE,
+ .pfn = __phys_to_pfn(AT91RM9200_SRAM_BASE),
+ .length = AT91RM9200_SRAM_SIZE,
.type = MT_DEVICE,
},
};
-void __init at91rm9200_map_io(void)
+/* --------------------------------------------------------------------
+ * Clocks
+ * -------------------------------------------------------------------- */
+
+/*
+ * The peripheral clocks.
+ */
+static struct clk udc_clk = {
+ .name = "udc_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_UDP,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ohci_clk = {
+ .name = "ohci_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_UHP,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk ether_clk = {
+ .name = "ether_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_EMAC,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk mmc_clk = {
+ .name = "mci_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_MCI,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk twi_clk = {
+ .name = "twi_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_TWI,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart0_clk = {
+ .name = "usart0_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_US0,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart1_clk = {
+ .name = "usart1_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_US1,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart2_clk = {
+ .name = "usart2_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_US2,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk usart3_clk = {
+ .name = "usart3_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_US3,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk spi_clk = {
+ .name = "spi_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_SPI,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioA_clk = {
+ .name = "pioA_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_PIOA,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioB_clk = {
+ .name = "pioB_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_PIOB,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioC_clk = {
+ .name = "pioC_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_PIOC,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+static struct clk pioD_clk = {
+ .name = "pioD_clk",
+ .pmc_mask = 1 << AT91RM9200_ID_PIOD,
+ .type = CLK_TYPE_PERIPHERAL,
+};
+
+static struct clk *periph_clocks[] __initdata = {
+ &pioA_clk,
+ &pioB_clk,
+ &pioC_clk,
+ &pioD_clk,
+ &usart0_clk,
+ &usart1_clk,
+ &usart2_clk,
+ &usart3_clk,
+ &mmc_clk,
+ &udc_clk,
+ &twi_clk,
+ &spi_clk,
+ // ssc 0 .. ssc2
+ // tc0 .. tc5
+ &ohci_clk,
+ ðer_clk,
+ // irq0 .. irq6
+};
+
+/*
+ * The four programmable clocks.
+ * You must configure pin multiplexing to bring these signals out.
+ */
+static struct clk pck0 = {
+ .name = "pck0",
+ .pmc_mask = AT91_PMC_PCK0,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 0,
+};
+static struct clk pck1 = {
+ .name = "pck1",
+ .pmc_mask = AT91_PMC_PCK1,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 1,
+};
+static struct clk pck2 = {
+ .name = "pck2",
+ .pmc_mask = AT91_PMC_PCK2,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 2,
+};
+static struct clk pck3 = {
+ .name = "pck3",
+ .pmc_mask = AT91_PMC_PCK3,
+ .type = CLK_TYPE_PROGRAMMABLE,
+ .id = 3,
+};
+
+static void __init at91rm9200_register_clocks(void)
{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(periph_clocks); i++)
+ clk_register(periph_clocks[i]);
+
+ clk_register(&pck0);
+ clk_register(&pck1);
+ clk_register(&pck2);
+ clk_register(&pck3);
+}
+
+
+/* --------------------------------------------------------------------
+ * AT91RM9200 processor initialization
+ * -------------------------------------------------------------------- */
+void __init at91rm9200_initialize(unsigned long main_clock)
+{
+ /* Map peripherals */
iotable_init(at91rm9200_io_desc, ARRAY_SIZE(at91rm9200_io_desc));
+
+ /* Init clock subsystem */
+ at91_clock_init(main_clock);
+
+ /* Register the processor-specific clocks */
+ at91rm9200_register_clocks();
}
/*
projects / powerpc.git / blobdiff