#define MMCONFIG_APER_MIN (2 * 1024*1024)
#define MMCONFIG_APER_MAX (256 * 1024*1024)
-/* Verify the first 16 busses. We assume that systems with more busses
- get MCFG right. */
-#define PCI_MMCFG_MAX_CHECK_BUS 16
-
DECLARE_BITMAP(pci_mmcfg_fallback_slots, 32*PCI_MMCFG_MAX_CHECK_BUS);
/* K8 systems have some devices (typically in the builtin northbridge)
and assigning suitable _SEGs, but this isn't implemented in some BIOS.
Instead try to discover all devices on bus 0 that are unreachable using MM
and fallback for them. */
-static __init void unreachable_devices(void)
+static void __init unreachable_devices(void)
{
- int i, k;
+ int i, bus;
/* Use the max bus number from ACPI here? */
- for (k = 0; k < PCI_MMCFG_MAX_CHECK_BUS; k++) {
+ for (bus = 0; bus < PCI_MMCFG_MAX_CHECK_BUS; bus++) {
for (i = 0; i < 32; i++) {
+ unsigned int devfn = PCI_DEVFN(i, 0);
u32 val1, val2;
- pci_conf1_read(0, k, PCI_DEVFN(i,0), 0, 4, &val1);
+ pci_conf1_read(0, bus, devfn, 0, 4, &val1);
if (val1 == 0xffffffff)
continue;
- raw_pci_ops->read(0, k, PCI_DEVFN(i, 0), 0, 4, &val2);
- if (val1 != val2) {
- set_bit(i + 32*k, pci_mmcfg_fallback_slots);
- printk(KERN_NOTICE "PCI: No mmconfig possible"
- " on device %02x:%02x\n", k, i);
+ if (pci_mmcfg_arch_reachable(0, bus, devfn)) {
+ raw_pci_ops->read(0, bus, devfn, 0, 4, &val2);
+ if (val1 == val2)
+ continue;
}
+ set_bit(i + 32 * bus, pci_mmcfg_fallback_slots);
+ printk(KERN_NOTICE "PCI: No mmconfig possible on device"
+ " %02x:%02x\n", bus, i);
}
}
}
-static __init const char *pci_mmcfg_e7520(void)
+static const char __init *pci_mmcfg_e7520(void)
{
u32 win;
pci_conf1_read(0, 0, PCI_DEVFN(0,0), 0xce, 2, &win);
return "Intel Corporation E7520 Memory Controller Hub";
}
-static __init const char *pci_mmcfg_intel_945(void)
+static const char __init *pci_mmcfg_intel_945(void)
{
u32 pciexbar, mask = 0, len = 0;
const char *(*probe)(void);
};
-static __initdata struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] = {
+static struct pci_mmcfg_hostbridge_probe pci_mmcfg_probes[] __initdata = {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, pci_mmcfg_e7520 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945G_HB, pci_mmcfg_intel_945 },
};
pci_mmcfg_config = NULL;
name = NULL;
- for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++)
- if ((pci_mmcfg_probes[i].vendor == PCI_ANY_ID ||
- pci_mmcfg_probes[i].vendor == vendor) &&
- (pci_mmcfg_probes[i].device == PCI_ANY_ID ||
- pci_mmcfg_probes[i].device == device))
+ for (i = 0; !name && i < ARRAY_SIZE(pci_mmcfg_probes); i++) {
+ if (pci_mmcfg_probes[i].vendor == vendor &&
+ pci_mmcfg_probes[i].device == device)
name = pci_mmcfg_probes[i].probe();
+ }
if (name) {
- if (pci_mmcfg_config_num)
- printk(KERN_INFO "PCI: Found %s with MMCONFIG support.\n", name);
- else
- printk(KERN_INFO "PCI: Found %s without MMCONFIG support.\n",
- name);
+ printk(KERN_INFO "PCI: Found %s %s MMCONFIG support.\n",
+ name, pci_mmcfg_config_num ? "with" : "without");
}
return name != NULL;
}
-static __init void pci_mmcfg_insert_resources(void)
+static void __init pci_mmcfg_insert_resources(void)
{
#define PCI_MMCFG_RESOURCE_NAME_LEN 19
int i;
res = kcalloc(PCI_MMCFG_RESOURCE_NAME_LEN + sizeof(*res),
pci_mmcfg_config_num, GFP_KERNEL);
-
if (!res) {
printk(KERN_ERR "PCI: Unable to allocate MMCONFIG resources\n");
return;
names = (void *)&res[pci_mmcfg_config_num];
for (i = 0; i < pci_mmcfg_config_num; i++, res++) {
- num_buses = pci_mmcfg_config[i].end_bus_number -
- pci_mmcfg_config[i].start_bus_number + 1;
+ struct acpi_mcfg_allocation *cfg = &pci_mmcfg_config[i];
+ num_buses = cfg->end_bus_number - cfg->start_bus_number + 1;
res->name = names;
snprintf(names, PCI_MMCFG_RESOURCE_NAME_LEN, "PCI MMCONFIG %u",
- pci_mmcfg_config[i].pci_segment);
- res->start = pci_mmcfg_config[i].address;
+ cfg->pci_segment);
+ res->start = cfg->address;
res->end = res->start + (num_buses << 20) - 1;
res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
insert_resource(&iomem_resource, res);
}
}
+static void __init pci_mmcfg_reject_broken(int type)
+{
+ typeof(pci_mmcfg_config[0]) *cfg;
+
+ if ((pci_mmcfg_config_num == 0) ||
+ (pci_mmcfg_config == NULL) ||
+ (pci_mmcfg_config[0].address == 0))
+ return;
+
+ cfg = &pci_mmcfg_config[0];
+
+ /*
+ * Handle more broken MCFG tables on Asus etc.
+ * They only contain a single entry for bus 0-0.
+ */
+ if (pci_mmcfg_config_num == 1 &&
+ cfg->pci_segment == 0 &&
+ (cfg->start_bus_number | cfg->end_bus_number) == 0) {
+ printk(KERN_ERR "PCI: start and end of bus number is 0. "
+ "Rejected as broken MCFG.\n");
+ goto reject;
+ }
+
+ /*
+ * Only do this check when type 1 works. If it doesn't work
+ * assume we run on a Mac and always use MCFG
+ */
+ if (type == 1 && !e820_all_mapped(cfg->address,
+ cfg->address + MMCONFIG_APER_MIN,
+ E820_RESERVED)) {
+ printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not"
+ " E820-reserved\n", cfg->address);
+ goto reject;
+ }
+ return;
+
+reject:
+ printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
+ kfree(pci_mmcfg_config);
+ pci_mmcfg_config = NULL;
+ pci_mmcfg_config_num = 0;
+}
+
void __init pci_mmcfg_init(int type)
{
int known_bridge = 0;
if (type == 1 && pci_mmcfg_check_hostbridge())
known_bridge = 1;
- if (!known_bridge)
+ if (!known_bridge) {
acpi_table_parse(ACPI_SIG_MCFG, acpi_parse_mcfg);
+ pci_mmcfg_reject_broken(type);
+ }
if ((pci_mmcfg_config_num == 0) ||
(pci_mmcfg_config == NULL) ||
(pci_mmcfg_config[0].address == 0))
return;
- /* Only do this check when type 1 works. If it doesn't work
- assume we run on a Mac and always use MCFG */
- if (type == 1 && !known_bridge &&
- !e820_all_mapped(pci_mmcfg_config[0].address,
- pci_mmcfg_config[0].address + MMCONFIG_APER_MIN,
- E820_RESERVED)) {
- printk(KERN_ERR "PCI: BIOS Bug: MCFG area at %Lx is not E820-reserved\n",
- pci_mmcfg_config[0].address);
- printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
- return;
- }
-
if (pci_mmcfg_arch_init()) {
if (type == 1)
unreachable_devices();
projects / powerpc.git / blobdiff