[POWERPC] of_detach_node()'s device node argument cannot be const

[powerpc.git] / arch / mips / Kconfig

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index a00fabe..1e3aecc 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -117,9 +117,9 @@ config MACH_JAZZ
        select ARC32
        select ARCH_MAY_HAVE_PC_FDC
        select GENERIC_ISA_DMA
-       select I8253
        select I8259
        select ISA
+       select PCSPEAKER
        select SYS_HAS_CPU_R4X00
        select SYS_SUPPORTS_32BIT_KERNEL
        select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
@@ -347,9 +347,9 @@ config QEMU
        select DMA_COHERENT
        select GENERIC_ISA_DMA
        select HAVE_STD_PC_SERIAL_PORT
-       select I8253
        select I8259
        select ISA
+       select PCSPEAKER
        select SWAP_IO_SPACE
        select SYS_HAS_CPU_MIPS32_R1
        select SYS_SUPPORTS_32BIT_KERNEL
@@ -562,9 +562,9 @@ config SNI_RM
        select HW_HAS_EISA
        select HW_HAS_PCI
        select IRQ_CPU
-       select I8253
        select I8259
        select ISA
+       select PCSPEAKER
        select SWAP_IO_SPACE if CPU_BIG_ENDIAN
        select SYS_HAS_CPU_R4X00
        select SYS_HAS_CPU_R5000
@@ -1190,8 +1190,19 @@ config SYS_HAS_CPU_RM9000
 config SYS_HAS_CPU_SB1
        bool
 
+#
+# CPU may reorder R->R, R->W, W->R, W->W
+# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
+#
 config WEAK_ORDERING
        bool
+
+#
+# CPU may reorder reads and writes beyond LL/SC
+# CPU may reorder R->LL, R->LL, W->LL, W->LL, R->SC, R->SC, W->SC, W->SC
+#
+config WEAK_REORDERING_BEYOND_LLSC
+       bool
 endmenu
 
 #
@@ -1404,6 +1415,19 @@ config MIPS_MT_SMTC_INSTANT_REPLAY
          it off), but ensures that IPIs are handled promptly even under
          heavy I/O interrupt load.
 
+config MIPS_MT_SMTC_IM_BACKSTOP
+       bool "Use per-TC register bits as backstop for inhibited IM bits"
+       depends on MIPS_MT_SMTC
+       default y
+       help
+         To support multiple TC microthreads acting as "CPUs" within
+         a VPE, VPE-wide interrupt mask bits must be specially manipulated
+         during interrupt handling. To support legacy drivers and interrupt
+         controller management code, SMTC has a "backstop" to track and
+         if necessary restore the interrupt mask. This has some performance
+         impact on interrupt service overhead. Disable it only if you know
+         what you are doing.
+
 config MIPS_VPE_LOADER_TOM
        bool "Load VPE program into memory hidden from linux"
        depends on MIPS_VPE_LOADER
@@ -1851,7 +1875,7 @@ config MMU
        bool
        default y
 
-config I8253
+config PCSPEAKER
        bool
 
 source "drivers/pcmcia/Kconfig"