PNX8550 uses a MIPS32-like processor core, not R4xx0.

[powerpc.git] / arch / mips / kernel / cpu-probe.c

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 844126b..a263fb7 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -121,6 +121,7 @@ static inline void check_wait(void)
        case CPU_24K:
        case CPU_25KF:
        case CPU_34K:
+       case CPU_PR4450:
                cpu_wait = r4k_wait;
                printk(" available.\n");
                break;
@@ -190,7 +191,7 @@ static inline int __cpu_has_fpu(void)
        return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
 }
 
-#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4KTLB \
+#define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
                | MIPS_CPU_COUNTER)
 
 static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
@@ -199,7 +200,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
        case PRID_IMP_R2000:
                c->cputype = CPU_R2000;
                c->isa_level = MIPS_CPU_ISA_I;
-               c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
+               c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
+                            MIPS_CPU_NOFPUEX;
                if (__cpu_has_fpu())
                        c->options |= MIPS_CPU_FPU;
                c->tlbsize = 64;
@@ -213,7 +215,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
                else
                        c->cputype = CPU_R3000;
                c->isa_level = MIPS_CPU_ISA_I;
-               c->options = MIPS_CPU_TLB | MIPS_CPU_NOFPUEX;
+               c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
+                            MIPS_CPU_NOFPUEX;
                if (__cpu_has_fpu())
                        c->options |= MIPS_CPU_FPU;
                c->tlbsize = 64;
@@ -276,7 +279,8 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
        case PRID_IMP_R4600:
                c->cputype = CPU_R4600;
                c->isa_level = MIPS_CPU_ISA_III;
-               c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
+               c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
+                            MIPS_CPU_LLSC;
                c->tlbsize = 48;
                break;
        #if 0
@@ -295,7 +299,7 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c)
        #endif
        case PRID_IMP_TX39:
                c->isa_level = MIPS_CPU_ISA_I;
-               c->options = MIPS_CPU_TLB;
+               c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
 
                if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
                        c->cputype = CPU_TX3927;
@@ -439,7 +443,7 @@ static inline unsigned int decode_config0(struct cpuinfo_mips *c)
        config0 = read_c0_config();
 
        if (((config0 & MIPS_CONF_MT) >> 7) == 1)
-               c->options |= MIPS_CPU_TLB | MIPS_CPU_4KTLB;
+               c->options |= MIPS_CPU_TLB;
        isa = (config0 & MIPS_CONF_AT) >> 13;
        switch (isa) {
        case 0:
@@ -514,8 +518,8 @@ static inline unsigned int decode_config3(struct cpuinfo_mips *c)
 static inline void decode_configs(struct cpuinfo_mips *c)
 {
        /* MIPS32 or MIPS64 compliant CPU.  */
-       c->options = MIPS_CPU_4KEX | MIPS_CPU_COUNTER | MIPS_CPU_DIVEC |
-                    MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
+       c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
+                    MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
 
        c->scache.flags = MIPS_CACHE_NOT_PRESENT;
 
@@ -544,6 +548,7 @@ static inline void cpu_probe_mips(struct cpuinfo_mips *c)
                c->cputype = CPU_4KEC;
                break;
        case PRID_IMP_4KSC:
+       case PRID_IMP_4KSD:
                c->cputype = CPU_4KSC;
                break;
        case PRID_IMP_5KC:
@@ -601,6 +606,15 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c)
 static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 {
        decode_configs(c);
+
+       /*
+        * For historical reasons the SB1 comes with it's own variant of
+        * cache code which eventually will be folded into c-r4k.c.  Until
+        * then we pretend it's got it's own cache architecture.
+        */
+       c->options &= ~MIPS_CPU_4K_CACHE;
+       c->options |= MIPS_CPU_SB1_CACHE;
+
        switch (c->processor_id & 0xff00) {
        case PRID_IMP_SB1:
                c->cputype = CPU_SB1;
@@ -609,6 +623,9 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
                c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
 #endif
                break;
+       case PRID_IMP_SB1A:
+               c->cputype = CPU_SB1A;
+               break;
        }
 }
 
@@ -624,6 +641,21 @@ static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c)
        }
 }
 
+static inline void cpu_probe_philips(struct cpuinfo_mips *c)
+{
+       decode_configs(c);
+       switch (c->processor_id & 0xff00) {
+       case PRID_IMP_PR4450:
+               c->cputype = CPU_PR4450;
+               c->isa_level = MIPS_CPU_ISA_M32;
+               break;
+       default:
+               panic("Unknown Philips Core!"); /* REVISIT: die? */
+               break;
+       }
+}
+
+
 __init void cpu_probe(void)
 {
        struct cpuinfo_mips *c = &current_cpu_data;
@@ -649,6 +681,9 @@ __init void cpu_probe(void)
        case PRID_COMP_SANDCRAFT:
                cpu_probe_sandcraft(c);
                break;
+       case PRID_COMP_PHILIPS:
+               cpu_probe_philips(c);
+               break;
        default:
                c->cputype = CPU_UNKNOWN;
        }